Patents by Inventor Srinivas Guggilla
Srinivas Guggilla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240090213Abstract: A method of forming a semiconductor memory device includes simultaneously filling a top portion of a first high aspect ratio (HAR) structure and a top portion a second HAR structure with a silicon-containing sacrificial layer by a cycle of a deposition process and an etch process, wherein the first HAR structure has a critical dimension (CD) of between 150 nm and 250 nm, and the second HAR structure has a CD of between 250 nm and 400 nm.Type: ApplicationFiled: August 28, 2023Publication date: March 14, 2024Inventors: Jialiang WANG, Soonil LEE, Eswaranand VENKATASUBRAMANIAN, Chang Seok KANG, Sanjay G. KAMATH, Abhijit B. MALLICK, Srinivas GUGGILLA, Amy CHILD, Sung-Kwan KANG, Balasubramanian PRANATHARTHIHARAN
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Publication number: 20240038833Abstract: Memory devices and methods of forming memory devices are described. Methods of forming electronic devices are described where carbon is used as the removable mold material for the formation of a DRAM capacitor. A dense, high-temperature (500° C. or greater) PECVD carbon material is used as the removable mold material, e.g., the core material, instead of oxide. The carbon material can be removed by isotropic etching with exposure to radicals of oxygen (O2), nitrogen (N2), hydrogen (H2), ammonia (NH3), and combinations thereof.Type: ApplicationFiled: July 14, 2023Publication date: February 1, 2024Applicant: Applied Materials, Inc.Inventors: Fredrick Fishburn, Tomohiko Kitajima, Qian Fu, Srinivas Guggilla, Hang Yu, Jun Feng, Shih Chung Chen, Lakmal C. Kalutarage, Jayden Potter, Karthik Janakiraman, Deenesh Padhi, Yifeng Zhou, Yufeng Jiang, Sung-Kwan Kang
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Publication number: 20230093450Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.Type: ApplicationFiled: November 30, 2022Publication date: March 23, 2023Inventors: Tzu-shun YANG, Rui CHENG, Karthik JANAKIRAMAN, Zubin HUANG, Diwakar KEDLAYA, Meenakshi GUPTA, Srinivas GUGGILLA, Yung-chen LIN, Hidetaka OSHIO, Chao LI, Gene LEE
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Patent number: 11569257Abstract: Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.Type: GrantFiled: May 29, 2020Date of Patent: January 31, 2023Assignee: Applied Materials, Inc.Inventors: Xinhai Han, Deenesh Padhi, Er-Xuan Ping, Srinivas Guggilla
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Patent number: 11527408Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.Type: GrantFiled: May 5, 2020Date of Patent: December 13, 2022Assignee: Applied Materials, Inc.Inventors: Tzu-shun Yang, Rui Cheng, Karthik Janakiraman, Zubin Huang, Diwakar Kedlaya, Meenakshi Gupta, Srinivas Guggilla, Yung-chen Lin, Hidetaka Oshio, Chao Li, Gene Lee
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Patent number: 11456173Abstract: Embodiments for processing a substrate are provided and include a method of trimming photoresist to provide photoresist profiles with smooth sidewall surfaces and to tune critical dimensions (CD) for the patterned features and/or a subsequently deposited dielectric layer. The method can include depositing a sacrificial structure layer on the substrate, depositing a photoresist on the sacrificial structure layer, and patterning the photoresist to produce a crude photoresist profile on the sacrificial structure layer. The method also includes trimming the photoresist with a plasma to produce a refined photoresist profile covering a first portion of the sacrificial structure layer while a second portion of the sacrificial structure layer is exposed, etching the second portion of the sacrificial structure layer to form patterned features disposed on the substrate, and depositing a dielectric layer on the patterned features.Type: GrantFiled: February 21, 2020Date of Patent: September 27, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Meenakshi Gupta, Rui Cheng, Srinivas Guggilla, Karthik Janakiraman, Diwakar N. Kedlaya, Zubin Huang
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Patent number: 11315787Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a mandrel layer on a substrate, conformally forming a spacer layer on the mandrel layer, wherein the spacer layer is a doped silicon material, and patterning the spacer layer. In another embodiment, a method for forming features on a substrate includes conformally forming a spacer layer on a mandrel layer on a substrate, wherein the spacer layer is a doped silicon material, selectively removing a portion of the spacer layer using a first gas mixture, and selectively removing the mandrel layer using a second gas mixture different from the first gas mixture.Type: GrantFiled: March 17, 2020Date of Patent: April 26, 2022Assignee: Applied Materials, Inc.Inventors: Tzu-shun Yang, Rui Cheng, Karthik Janakiraman, Zubin Huang, Diwakar Kedlaya, Meenakshi Gupta, Srinivas Guggilla, Yung-chen Lin, Hidetaka Oshio, Chao Li, Gene Lee
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Patent number: 11101117Abstract: Embodiments of a method and apparatus for co-sputtering multiple target materials are provided herein. In some embodiments, a process chamber including a substrate support to support a substrate; a plurality of cathodes coupled to a carrier and having a corresponding plurality of targets to be sputtered onto the substrate; and a process shield coupled to the carrier and extending between adjacent pairs of the plurality of targets.Type: GrantFiled: September 17, 2019Date of Patent: August 24, 2021Assignee: APPLIED MATERIALS, INC.Inventors: Anantha K. Subramani, Hanbing Wu, Wei W. Wang, Ashish Goel, Srinivas Guggilla, Lavinia Nistor
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Publication number: 20200335339Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.Type: ApplicationFiled: May 5, 2020Publication date: October 22, 2020Inventors: Tzu-shun YANG, Rui CHENG, Karthik JANAKIRAMAN, Zubin HUANG, Diwakar KEDLAYA, Meenakshi GUPTA, Srinivas GUGGILLA, Yung-chen LIN, Hidetaka OSHIO, Chao LI, Gene LEE
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Publication number: 20200335338Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a mandrel layer on a substrate, conformally forming a spacer layer on the mandrel layer, wherein the spacer layer is a doped silicon material, and patterning the spacer layer. In another embodiment, a method for forming features on a substrate includes conformally forming a spacer layer on a mandrel layer on a substrate, wherein the spacer layer is a doped silicon material, selectively removing a portion of the spacer layer using a first gas mixture, and selectively removing the mandrel layer using a second gas mixture different from the first gas mixture.Type: ApplicationFiled: March 17, 2020Publication date: October 22, 2020Inventors: Tzu-Shun YANG, Rui CHENG, Karthik JANAKIRAMAN, Zubin HUANG, Diwakar KADLAYA, Meenakshi GUPTA, Srinivas GUGGILLA, Yung-chen LIN, Hidetaka OSHIO, Chao LI, Gene LEE
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Publication number: 20200321210Abstract: Embodiments for processing a substrate are provided and include a method of trimming photoresist to provide photoresist profiles with smooth sidewall surfaces and to tune critical dimensions (CD) for the patterned features and/or a subsequently deposited dielectric layer. The method can include depositing a sacrificial structure layer on the substrate, depositing a photoresist on the sacrificial structure layer, and patterning the photoresist to produce a crude photoresist profile on the sacrificial structure layer. The method also includes trimming the photoresist with a plasma to produce a refined photoresist profile covering a first portion of the sacrificial structure layer while a second portion of the sacrificial structure layer is exposed, etching the second portion of the sacrificial structure layer to form patterned features disposed on the substrate, and depositing a dielectric layer on the patterned features.Type: ApplicationFiled: February 21, 2020Publication date: October 8, 2020Inventors: Meenakshi GUPTA, Rui CHENG, Srinivas GUGGILLA, Karthik JANAKIRAMAN, Diwakar N. KEDLAYA, Zubin HUANG
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Publication number: 20200295041Abstract: Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.Type: ApplicationFiled: May 29, 2020Publication date: September 17, 2020Inventors: Xinhai HAN, Deenesh PADHI, Er-Xuan PING, Srinivas GUGGILLA
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Patent number: 10707122Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.Type: GrantFiled: September 24, 2018Date of Patent: July 7, 2020Assignee: APPLIED MATERIALS, INC.Inventors: Sree Rangasai V. Kesapragada, Kevin Moraes, Srinivas Guggilla, He Ren, Mehul Naik, David Thompson, Weifeng Ye, Yana Cheng, Yong Cao, Xianmin Tang, Paul F. Ma, Deenesh Padhi
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Patent number: 10700087Abstract: Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.Type: GrantFiled: October 4, 2018Date of Patent: June 30, 2020Assignee: APPLIED MATERIALS, INC.Inventors: Xinhai Han, Deenesh Padhi, Er-Xuan Ping, Srinivas Guggilla
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Publication number: 20200013597Abstract: Embodiments of a method and apparatus for co-sputtering multiple target materials are provided herein. In some embodiments, a process chamber including a substrate support to support a substrate; a plurality of cathodes coupled to a carrier and having a corresponding plurality of targets to be sputtered onto the substrate; and a process shield coupled to the carrier and extending between adjacent pairs of the plurality of targets.Type: ApplicationFiled: September 17, 2019Publication date: January 9, 2020Inventors: Anantha K. SUBRAMANI, Hanbing WU, Wei W. WANG, Ashish GOEL, Srinivas GUGGILLA, Lavinia NISTOR
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Publication number: 20190348369Abstract: A method and apparatus for forming an interconnect on a substrate is provided. A protective layer is formed on the substrate and in a via formed on the substrate wherein the protective layer is resistant to a halogen containing material. A barrier layer is formed on top of the protective layer. The barrier layer comprises a halogen containing material. A metal layer is deposited over the barrier layer. In another embodiment, the protective layer is selectively deposited in the via.Type: ApplicationFiled: May 10, 2018Publication date: November 14, 2019Inventors: Mehul B. NAIK, Paul F. MA, Tae Hong HA, Srinivas GUGGILLA
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Patent number: 10468238Abstract: Embodiments of a method and apparatus for co-sputtering multiple target materials are provided herein. In some embodiments, a process chamber including a substrate support to support a substrate; a plurality of cathodes coupled to a carrier and having a corresponding plurality of targets to be sputtered onto the substrate; and a process shield coupled to the carrier and extending between adjacent pairs of the plurality of targets.Type: GrantFiled: August 18, 2016Date of Patent: November 5, 2019Assignee: APPLIED MATERIALS, INC.Inventors: Anantha K. Subramani, Hanbing Wu, Wei W. Wang, Ashish Goel, Srinivas Guggilla, Lavinia Nistor
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Publication number: 20190115365Abstract: Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.Type: ApplicationFiled: October 4, 2018Publication date: April 18, 2019Inventors: Xinhai HAN, Deenesh PADHI, Er-Xuan PING, Srinivas GUGGILLA
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Publication number: 20190027403Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.Type: ApplicationFiled: September 24, 2018Publication date: January 24, 2019Inventors: Sree Rangasai V. KESAPRAGADA, Kevin MORAES, Srinivas GUGGILLA, He REN, Mehul NAIK, David THOMPSON, Weifeng YE, Yana CHENG, Yong CAO, Xianmin TANG, Paul F. MA, Deenesh PADHI
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Patent number: 10109520Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.Type: GrantFiled: October 4, 2016Date of Patent: October 23, 2018Assignee: APPLIED MATERIALS, INC.Inventors: Sree Rangasai V. Kesapragada, Kevin Moraes, Srinivas Guggilla, He Ren, Mehul Naik, David Thompson, Weifeng Ye, Yana Cheng, Yong Cao, Xianmin Tang, Paul F. Ma, Deenesh Padhi