Patents by Inventor Srinivas Jallepalli
Srinivas Jallepalli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9940418Abstract: This disclosure describes a design tool that iteratively performs simulation sets on an integrated circuit design, each corresponding to a different hierarchical level with each of the simulation sets producing a different set of simulation results. Each of the simulation sets utilizes a different set of local parameter values that include extreme instance local parameter values based on the set of simulation results of a preceding simulation set. The design tool generates a set of hierarchically aggregated simulation results based upon the last set of simulation results and global parameters, and modifies the integrated circuit design based upon a yield estimation that is determined from comparing the set of hierarchically aggregated simulation results to specification requirements that correspond to the integrated circuit design.Type: GrantFiled: July 22, 2015Date of Patent: April 10, 2018Assignee: NXP USA, Inc.Inventors: Srinivas Jallepalli, Jon S. Choy
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Publication number: 20170024502Abstract: This disclosure describes a design tool that iteratively performs simulation sets on an integrated circuit design, each corresponding to a different hierarchical level with each of the simulation sets producing a different set of simulation results. Each of the simulation sets utilizes a different set of local parameter values that include extreme instance local parameter values based on the set of simulation results of a preceding simulation set. The design tool generates a set of hierarchically aggregated simulation results based upon the last set of simulation results and global parameters, and modifies the integrated circuit design based upon a yield estimation that is determined from comparing the set of hierarchically aggregated simulation results to specification requirements that correspond to the integrated circuit design.Type: ApplicationFiled: July 22, 2015Publication date: January 26, 2017Inventors: Srinivas Jallepalli, Jon S. Choy
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Patent number: 8806418Abstract: A method can include generating a first set of sample values for input variables in accordance with a prescribed set of probability distributions, running a set of simulations on an electronic component based upon the first set of sample values, multiplying the standard deviations of the original distributions by a scaling factor ?, generating a second set of sample values for the input variables based on the probability distributions thus generated, and running a set of simulations on the electronic component based on this second set of sample values. The method can also include the generation of Q-Q plots based on the data from the first and second set of simulations and data from a truly normal distribution or the distribution obeyed by the independently varying input parameters; and the use of these plots for assessment of the robustness and functionality of the electronic component.Type: GrantFiled: June 19, 2013Date of Patent: August 12, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Srinivas Jallepalli, Earl K. Hunter, Elie A. Maalouf, Venkataram M. Mooraka, Sanjay R. Parihar
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Publication number: 20050156229Abstract: A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.Type: ApplicationFiled: December 16, 2004Publication date: July 21, 2005Inventors: Geoffrey Yeap, Srinivas Jallepalli, Yongjoo Jeon, James Burnett, Rana Singh, Paul Grudowski
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Patent number: 6846716Abstract: A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.Type: GrantFiled: December 16, 2003Date of Patent: January 25, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Geoffrey C-F Yeap, Srinivas Jallepalli, Yongjoo Jeon, James David Burnett, Rana P. Singh, Paul A. Grudowski
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Publication number: 20040124450Abstract: A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.Type: ApplicationFiled: December 16, 2003Publication date: July 1, 2004Inventors: Geoffrey C-F Yeap, Srinivas Jallepalli, Yongjoo Jeon, James David Burnett, Rana P. Singh, Paul A. Grudowski
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Patent number: 6753242Abstract: A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.Type: GrantFiled: March 19, 2002Date of Patent: June 22, 2004Assignee: Motorola, Inc.Inventors: Geoffrey C-F Yeap, Srinivas Jallepalli, Yongjoo Jeon
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Publication number: 20030181028Abstract: A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.Type: ApplicationFiled: March 19, 2002Publication date: September 25, 2003Inventors: Geoffrey C-F Yeap, Srinivas Jallepalli, Yongjoo Jeon, James David Burnett, Rana P. Singh, Paul A. Grudowski
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Patent number: 6617214Abstract: An integrated circuit is made with transistors having varying characteristics in the same well. One transistor, which is particularly useful as an I/O device, has a relatively deep source/drain with a relatively thick gate dielectric. The well doping is selected so that this transistor has low leakage. Another transistor type, which is particularly useful for low voltage analog purposes, has a relatively thin gate dielectric and the relatively deep source/drain. A third transistor type, which is particularly suited for high density and low power operation, has a relatively shallow source/drain, the relatively thin gate dielectric, and a high dose halo implant. A fourth transistor type, which may also be present for high-speed operations, has the relatively thin gate dielectric, the relatively shallow source/drain, and may have a halo implant. The halo implant will be of a lower dosage than the halo implant for the third transistor type.Type: GrantFiled: April 23, 2001Date of Patent: September 9, 2003Assignee: Motorola, Inc.Inventors: Choh-Fei Yeap, Srinivas Jallepalli, Alain C. Duvallet, Franklin D. Nkansah
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Publication number: 20020153559Abstract: An integrated circuit is made with transistors having varying characteristics in the same well. One transistor, which is particularly useful as an I/O device, has a relatively deep source/drain with a relatively thick gate dielectric. The well doping is selected so that this transistor has low leakage. Another transistor type, which is particularly useful for low voltage analog purposes, has a relatively thin gate dielectric and the relatively deep source/drain. A third transistor type, which is particularly suited for high density and low power operation, has a relatively shallow source/drain, the relatively thin gate dielectric, and a high dose halo implant. A fourth transistor type, which may also be present for high-speed operations, has the relatively thin gate dielectric, the relatively shallow source/drain, and may have a halo implant. The halo implant will be of a lower dosage than the halo implant for the third transistor type.Type: ApplicationFiled: April 23, 2001Publication date: October 24, 2002Inventors: Choh-Fei Yeap, Srinivas Jallepalli, Alain C. Duvallet, Franklin D. Nkansah