Abstract: Techniques and architecture are described to control a debug port access employing the debug image signed offline by a challenge/response mechanism, where the signed image itself is tied to an ECID of a chip together with debug lifecycle information coming from fuses and a hash of a loader being debugged. All these inputs form a nonce (the debug image) that ties the debug image to the hardware being debugged and is restricted to the current debug lifecycle. The cryptographically signed debug image is authenticated by a boot image (or the chip) with a public key in the debug image. The debug image may be expanded to secure maintenance using a secure maintenance blob or “firmware maintenance certificate or nonce.” The secure maintenance blob also includes a natural attribute list of low-level features to be enabled upon verification of the secure maintenance blob.

Abstract: In one embodiment, a method including transmitting data cells through a plurality of queues to an input of a processor is disclosed. The method includes transmitting data cells from an output of the processor to corresponding virtual circuits. The amount of data transmitted through each queue is computed. The cumulative amount of data transmitted through all queues is also computed. For each queue, a ratio of the amount of data transmitted through the queue to the cumulative amount of data transmitted through all queues is determined. The method also determines an amount of processor time for each queue using the ratio for the queue.