Abstract: Described examples include integrated circuits such as microcontrollers with a low energy accelerator processor circuit or other application specific integrated processor circuit including a load store circuit operative to perform load and store operations associated with at least one register and a low gate count shift circuit to selectively shift the data of the register by only an integer number of bits less than the register data width without using a barrel shifter for low power operation to support vector operations for FFT or filtering functions.

Abstract: An integrated circuit includes one or more central processing unit (CPU) cores configured to cause a first ultrasonic transducer to generate ultrasonic signals into a fluid moving in a pipe and the first or a second ultrasonic transducer to receive the ultrasonic signals from the fluid. The CPU core(s) also compute a first value indicative of at least one of a standard deviation and a time correlation based on the received ultrasonic signals. The CPU core(s) further determine a second value indicative of a volume of gas bubbles in the fluid using the computed first value indicative of the at least one of the standard deviation and time correlation.

Abstract: An integrated circuit includes one or more central processing unit (CPU) cores configured to cause a first ultrasonic transducer to generate ultrasonic signals into a fluid moving in a pipe and the first or a second ultrasonic transducer to receive the ultrasonic signals from the fluid. The CPU core(s) also compute a first value indicative of at least one of a standard deviation and a time correlation based on the received ultrasonic signals. The CPU core(s) further determine a second value indicative of a volume of gas bubbles in the fluid using the computed first value indicative of the at least one of the standard deviation and time correlation.

Abstract: A method of communicating a packet between a first node and a second node, the packet comprising a data payload and a portion of information preceding the data payload. The method comprises: (i) first, identifying a quality of a channel between the first node and the second node; (ii) second, in response to the quality of the channel, selecting a manner of communication of the information preceding the data payload; (iii) third, encoding the selected manner of communication in the portion of information preceding data payload; and (iv) fourth, transmitting the packet from the first node to the second node.

Abstract: Disclosed examples include methods and systems to measure fluid flow, including a transmit circuit to provide a transducer transmit signal based on a transmit pulse signal, a receive circuit to receive a transducer receive signal, an ADC to sample a receive signal from the receive circuit and provide a sampled signal, and a processing circuit that computes a transit time based on the sampled signal, and provides the transmit pulse signal including a first portion with a frequency in a first frequency band, and a second portion with a second frequency outside the first frequency band to mitigate undesired transducer vibration, where the second frequency is outside a transducer frequency bandwidth of the transducer.

Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

Abstract: An integrated circuit includes one or more central processing unit (CPU) cores configured to cause a first ultrasonic transducer to generate ultrasonic signals into a fluid moving in a pipe and the first or a second ultrasonic transducer to receive the ultrasonic signals from the fluid. The CPU core(s) also compute a first value indicative of at least one of a standard deviation and a time correlation based on the received ultrasonic signals. The CPU core(s) further determine a second value indicative of a volume of gas bubbles in the fluid using the computed first value indicative of the at least one of the standard deviation and time correlation.

Abstract: A method of communicating a packet between a first node and a second node, the packet comprising a data payload and a portion of information preceding the data payload. The method comprises: (i) first, identifying a quality of a channel between the first node and the second node; (ii) second, in response to the quality of the channel, selecting a manner of communication of the information preceding the data payload; (iii) third, encoding the selected manner of communication in the portion of information preceding data payload; and (iv) fourth, transmitting the packet from the first node to the second node.

Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

Abstract: A method of communicating a packet between a first node and a second node, the packet comprising a data payload and a portion of information preceding the data payload. The method comprises: (i) first, identifying a quality of a channel between the first node and the second node; (ii) second, in response to the quality of the channel, selecting a manner of communication of the information preceding the data payload; (iii) third, encoding the selected manner of communication in the portion of information preceding data payload; and (iv) fourth, transmitting the packet from the first node to the second node.

Abstract: Instructions for 32-bit arithmetic support using 16-bit multiply and 32-bit addition without a barrel shifter. Illustrative instructions include operations that include receiving a first 32-bit operand, receiving a second 32-bit operand, shifting the second 32-bit operand right 16 or 15 bits to obtain a shifted second 32-bit operand, and adding the shifted second 32-bit operand and the first 32-bit operand to generate a 32-bit sum.

Abstract: Instructions for 32-bit arithmetic support using 16-bit multiply and 32-bit addition without a barrel shifter. Illustrative instructions include operations that include receiving a first 32-bit operand, receiving a second 32-bit operand, shifting the second 32-bit operand right 16 or 15 bits to obtain a shifted second 32-bit operand, and adding the shifted second 32-bit operand and the first 32-bit operand to generate a 32-bit sum.

Abstract: Instructions for 32-bit arithmetic support using 16-bit multiply and 32-bit addition without a barrel shifter. Illustrative instructions include operations that include receiving a first 32-bit operand, receiving a second 32-bit operand, shifting the second 32-bit operand right 16 or 15 bits to obtain a shifted second 32-bit operand, and adding the shifted second 32-bit operand and the first 32-bit operand to generate a 32-bit sum.

Abstract: An apparatus for a low energy accelerator processor architecture is disclosed. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory; a low energy accelerator processor configured to execute instruction words received on the system bus and having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, wherein each of the execution units is configured to perform operations responsive to retrieved instruction words; and a data register file comprising a set of data registers coupled to the plurality of execution units, wherein the registers are coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.

Abstract: A method of communicating a packet between a first node and a second node, the packet comprising a data payload and a portion of information preceding the data payload. The method comprises: (i) first, identifying a quality of a channel between the first node and the second node; (ii) second, in response to the quality of the channel, selecting a manner of communication of the information preceding the data payload; (iii) third, encoding the selected manner of communication in the portion of information preceding data payload; and (iv) fourth, transmitting the packet from the first node to the second node.

Abstract: Disclosed examples include methods and systems to measure fluid flow, including a transmit circuit to provide a transducer transmit signal based on a transmit pulse signal, a receive circuit to receive a transducer receive signal, an ADC to sample a receive signal from the receive circuit and provide a sampled signal, and a processing circuit that computes a transit time based on the sampled signal, and provides the transmit pulse signal including a first portion with a frequency in a first frequency band, and a second portion with a second frequency outside the first frequency band to mitigate undesired transducer vibration, where the second frequency is outside a transducer frequency bandwidth of the transducer.

Abstract: A method of communicating a packet between a first node and a second node, the packet comprising a data payload and a portion of information preceding the data payload. The method comprises: (i) first, identifying a quality of a channel between the first node and the second node; (ii) second, in response to the quality of the channel, selecting a manner of communication of the information preceding the data payload; (iii) third, encoding the selected manner of communication in the portion of information preceding data payload; and (iv) fourth, transmitting the packet from the first node to the second node.

Abstract: An apparatus for a low energy accelerator processor architecture is disclosed. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory; a low energy accelerator processor configured to execute instruction words received on the system bus and having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, wherein each of the execution units is configured to perform operations responsive to retrieved instruction words; and a data register file comprising a set of data registers coupled to the plurality of execution units, wherein the registers are coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.

Abstract: A cascaded integrator-comb filter (CIC) that includes a differentiator, a rate changer, an integrator, and a multiplier. The differentiator is configured to differentiate an input signal to produce a differentiated input signal. The rate changer is coupled to the differentiator and is configured to interpolate the differentiated input signal based on an interpolation rate to produce an upsample signal. The integrator is coupled to the rate changer and is configured to integrate the upsample signal to produce an output signal. The multiplier is coupled to the differentiator, rate changer, and integrator and is configured to increase the output signal amplitude based on the interpolation rate.