Abstract: A system-on-a-chip (“SoC”) in a computing device may be provided with a power delivery network (“PDN”) self-test to detect marginal PDN performance. In the self-test, a current surge may be generated on power supply connections of logic circuit blocks. Voltage monitors may measure voltage droop on the power supply connections responsive to the current surge. Voltage droop measurements may be compared with thresholds. An action, such as generation of an alert, may be performed if a voltage droop measurement exceeds a threshold.

Abstract: A system-on-a-chip (“SoC”) in a computing device may be provided with a power delivery network (“PDN”) self-test to detect marginal PDN performance. In the self-test, a current surge may be generated on power supply connections of logic circuit blocks. Voltage monitors may measure voltage droop on the power supply connections responsive to the current surge. Voltage droop measurements may be compared with thresholds. An action, such as generation of an alert, may be performed if a voltage droop measurement exceeds a threshold.

Abstract: This disclosure describes an integrated circuit with self-test features for validating functionality of external interfaces. Example external interfaces include memory interfaces and bus interfaces, such as a peripheral component interconnect (PCI) bus, an advanced high-performance bus (AHB), an advanced extensible interface (AXI) bus, and other external interfaces that operate a high frequency, e.g., 200 MHz or greater. Test logic may be embedded on the integrated circuit and configured to validate functionality of external interfaces while receiving power and non-test signals from external test equipment. Thus, external test equipment may not supply high frequency test signals to the integrated circuit. The external test equipment may, however, independently validate functionality of a pin interface of the integrated circuit. As a result, the integrated circuit may reduce cost and time required to verify functionality and timing of the external interfaces.

Abstract: An arbiter detects waiting states of N buffers holding direct memory access (DMA) requests, and detects an availability of R core channels of a core R-channel DMA memory. The arbiter, based on the detection, dynamically grants up to R of the N buffers access to the R core channels. An N-to-R controller communicates DMA requests from the N buffers to currently granted ones of the R core channels, and maintains a location record of different data from each of the N buffers being written into different ones of the R core channels.

Abstract: A configurable memory access controller and related systems and methods. In embodiments described herein, the configurable memory controller is adapted to provide a separate memory access configuration for each of a plurality of memory banks in a given memory system. The memory access configuration provided for each memory bank can either be to leave open or close at least one memory page in each memory bank. In this manner, a memory access configuration can be provided for each memory bank on an individualized basis to optimize memory access times based on the type of data activity in each memory bank. In embodiments described herein, the memory controller can also be configured to allow for dynamic configuration of one or more memory banks. Dynamic configuration involves changing or overriding the memory access configuration for a particular memory bank to optimize memory access times.

Abstract: A method and apparatus for detecting the configuration of a device in a processing system are described. In one embodiment, a page size parameter associated with a memory device is identified. Further, one or more configuration parameters associated with the memory device are also identified, the page size parameter and the configuration parameters enabling access to the memory device. Finally, a request to download application data from the memory device based on the page size parameter and the one or more configuration parameters is transmitted to the memory device.

Abstract: A configurable memory access controller and related systems and methods. In embodiments described herein, the configurable memory controller is adapted to provide a separate memory access configuration for each of a plurality of memory banks in a given memory system. The memory access configuration provided for each memory bank can either be to leave open or close at least one memory page in each memory bank. In this manner, a memory access configuration can be provided for each memory bank on an individualized basis to optimize memory access times based on the type of data activity in each memory bank. In embodiments described herein, the memory controller can also be configured to allow for dynamic configuration of one or more memory banks. Dynamic configuration involves changing or overriding the memory access configuration for a particular memory bank to optimize memory access times.

Abstract: This disclosure describes a clock circuit for a memory controller. The described circuit uses a processor clock signal to generate an input clock signal for use during write operations to the memory, or to generate a feedback clock signal for use during read operations from the memory. The circuit is particularly applicable to mobile wireless devices that include memories that do not generate a strobe. The clock circuit may comprise a driver in series with a resistor element that generates an input clock signal for input to a memory, and a resistor-capacitor (RC) filter in series with a receiver that generates a feedback clock signal for output from the memory, wherein an input to the RC filter is tapped between the driver and the resistor element.

Abstract: This disclosure describes an integrated circuit with self-test features for validating functionality of external interfaces. Example external interfaces include memory interfaces and bus interfaces, such as a peripheral component interconnect (PCI) bus, an advanced high-performance bus (AHB), an advanced extensible interface (AXI) bus, and other external interfaces that operate a high frequency, e.g., 200 MHz or greater. Test logic may be embedded on the integrated circuit and configured to validate functionality of external interfaces while receiving power and non-test signals from external test equipment. Thus, external test equipment may not supply high frequency test signals to the integrated circuit. The external test equipment may, however, independently validate functionality of a pin interface of the integrated circuit. As a result, the integrated circuit may reduce cost and time required to verify functionality and timing of the external interfaces.

Abstract: This disclosure describes a clock circuit for a memory controller. The described circuit uses a processor clock signal to generate an input clock signal for use during write operations to the memory, or to generate a feedback clock signal for use during read operations from the memory. The circuit is particularly applicable to mobile wireless devices that include memories that do not generate a strobe. The clock circuit may comprise a driver in series with a resistor element that generates an input clock signal for input to a memory, and a resistor-capacitor (RC) filter in series with a receiver that generates a feedback clock signal for output from the memory, wherein an input to the RC filter is tapped between the driver and the resistor element.

Abstract: A method and apparatus for detecting the configuration of a device in a processing system are described. In one embodiment, a page size parameter associated with a memory device is identified. Further, one or more configuration parameters associated with the memory device are also identified, the page size parameter and the configuration parameters enabling access to the memory device. Finally, a request to download application data from the memory device based on the page size parameter and the one or more configuration parameters is transmitted to the memory device.

Abstract: Embodiments of the present invention illustrate various configurations of a channel-to-controller interface. In one embodiment, width of symbols crossing the interface is fixed, as is the clock rate. In other embodiments, the symbol width is variable, and the clock rate is also varied based upon the size of the interface symbol width and the operation of the channel.

Abstract: Embodiments of the present invention illustrate various configurations of a channel-to-controller interface. In one embodiment, width of symbols crossing the interface is fixed, as is the clock rate. In other embodiments, the symbol width is variable, and the clock rate is also varied based upon the size of the interface symbol width and the operation of the channel.