Abstract: This application discloses a computing system implementing tools and mechanisms that can incorporate a validation system into a circuit design. The validation system can be configured to monitor at least a portion of an electronic device described in the circuit design. The tools and mechanisms can identify one or more trace signals associated with the electronic device to route to the validation system, and identify one or more trigger signals associated with the electronic device to route to the validation system. The tools and mechanisms can configure the validation system to detect a conditional event corresponding a state of the one or more trigger signals, and to transmit the trace signals associated with the electronic device for debugging in response to the detected conditional event.

Abstract: This application discloses a system to detect meta-stable glitches in a signal, such as an output of latch or other storage element. The system can include a sampling circuit configured to sample an output of a storage element. The system can include a mono-shot circuit configured to monitor the output of the storage element and generate a pulse when the monitored output of the storage element differs from the sampled output. The system can include a drive circuit configured to generate a glitch signal based, at least in part, on the sampled output, and to output the glitch signal in response to the pulse from the mono-shot circuit. The system can include an error detection circuit configured to receive the sampled output from the sampling circuit and the glitch signal from the drive circuit, and to generate an error signal when the sampled output differs from the glitch signal.

Abstract: This application discloses a system to detect meta-stable glitches in a signal, such as an output of latch or other storage element. The system can include a sampling circuit configured to sample an output of a storage element. The system can include a mono-shot circuit configured to monitor the output of the storage element and generate a pulse when the monitored output of the storage element differs from the sampled output. The system can include a drive circuit configured to generate a glitch signal based, at least in part, on the sampled output, and to output the glitch signal in response to the pulse from the mono-shot circuit. The system can include an error detection circuit configured to receive the sampled output from the sampling circuit and the glitch signal from the drive circuit, and to generate an error signal when the sampled output differs from the glitch signal.

Abstract: This application discloses a computing system implementing tools and mechanisms that can incorporate a validation system into a circuit design. The validation system can be configured to monitor at least a portion of an electronic device described in the circuit design. The tools and mechanisms can identify one or more trace signals associated with the electronic device to route to the validation system, and identify one or more trigger signals associated with the electronic device to route to the validation system. The tools and mechanisms can configure the validation system to detect a conditional event corresponding a state of the one or more trigger signals, and to transmit the trace signals associated with the electronic device for debugging in response to the detected conditional event.

Abstract: This application discloses a system to detect meta-stable glitches in a signal, such as an output of latch or other storage element. The system can include a sampling circuit configured to sample an output of a storage element. The system can include a mono-shot circuit configured to monitor the output of the storage element and generate a pulse when the monitored output of the storage element differs from the sampled output. The system can include a drive circuit configured to generate a glitch signal based, at least in part, on the sampled output, and to output the glitch signal in response to the pulse from the mono-shot circuit. The system can include an error detection circuit configured to receive the sampled output from the sampling circuit and the glitch signal from the drive circuit, and to generate an error signal when the sampled output differs from the glitch signal.

Abstract: A copy of a design is stored at each of multiple clients. When a client user provides input indicating a wish to modify the design in some way, the input is captured and one or more commands created. The commands are forwarded to a server, which queues commands received from all of the clients and then forwards each of those commands back to each of the clients. Upon receiving commands from the server, each of the clients executes those commands in the order received. Each client also maintains data indicating settings for all clients in a current editing session. Before executing a design changing command, each client adjusts its settings to match those of the client from which that command originated.

Abstract: A copy of a design is stored at each of multiple clients. When a client user provides input indicating a wish to modify the design in some way, the input is captured and one or more commands created. The commands are forwarded to a server, which queues commands received from all of the clients and then forwards each of those commands back to each of the clients. Upon receiving commands from the server, each of the clients executes those commands in the order received. Each client also maintains data indicating settings for all clients in a current editing session. Before executing a design changing command, each client adjusts its settings to match those of the client from which that command originated.

Abstract: A method of operating a processor core provides of instructions for copying data from one general purpose register to another general purpose register. A conditional move instruction provides for conditional copying of bits from a source register into a destination based on corresponding bits in a control register. A permute instruction provides for arbitrary permutations based on a control register.

Abstract: A method is disclosed for effectuating multiplication in a processor core. The method supports multiplication instructions for two formats of data: integer-formatted data and fixed-point data, exclusive of a floating point unit. The data can be packed data, including 16-bit packed data and 32-bit packed data.