Patents by Inventor Srinivas Patil

Srinivas Patil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10383114
    Abstract: Improvement in co-existence of the LTE device-to-device communication with another device-to-device communication method is desired. The apparatus selects a countdown number within a size of a contention window including a plurality of slots before a target subframe. The apparatus determines whether each slot of the plurality of slots is idle or utilized while waiting for the target subframe. The apparatus counts down the countdown number during each of the determined idle slots. The apparatus determines whether the countdown number has reached a threshold number before the target subframe. The apparatus performs, when the countdown number is determined to have reached the threshold number, one of: deferring from transmitting until the target subframe, or transmitting a CUBS until a next subframe or the target subframe.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: August 13, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Libin Jiang, Shailesh Patil, Peter Gaal, Srinivas Yerramalli
  • Patent number: 10324131
    Abstract: The present disclosure provide techniques for semiconductor testing, and more particularly, to systems and methods for laser-based fault isolation and design for testability (DFT) diagnosis techniques. In one embodiment, an integrated chip (IC) testing apparatus, includes an input pin; a decompressor connected to the input pin; a plurality of scan chains, each scan chain of the plurality of scan chains comprising a plurality of scan cells; a plurality of scan chain control elements, each scan chain control element of the plurality of scan chain control elements being connected between the decompressor and a respective scan chain of the plurality of scan chains, wherein each scan chain control element is configured to enable or disable test data from flowing from the compressor to the respective scan chain; a compressor connected to an output of each scan chain of the plurality of scan chains; and an output pin connected to the compressor.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: June 18, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Lesly Endrinal, Rakesh Kinger, Joseph Fang, Srinivas Patil, Lavakumar Ranganathan, Chia-Ying Chen
  • Patent number: 9087037
    Abstract: A Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to the Test Wrappers via an interconnect fabric. The Test Wrappers employ one or more test ports to provide test data, control, and/or stimulus signals to the IP block to facilitate circuit-level testing of the IP block. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: July 21, 2015
    Assignee: Intel Corporation
    Inventors: Srinivas Patil, Abhijit Jas
  • Patent number: 9043665
    Abstract: A Test Wrapper and associated Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to one or more Test Wrappers via an interconnect fabric. The Test Wrappers interface with one or more IP test ports to provide test data, control, and/or stimulus signals to the IP blocks to facilitate circuit-level testing of the IP blocks. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: May 26, 2015
    Assignee: Intel Corporation
    Inventors: Srinivas Patil, Abhijit Jas, Peter Lisherness
  • Patent number: 8793095
    Abstract: A Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to the Test Wrappers via an interconnect fabric. The Test Wrappers employ interface with one or more test ports to provide test data, control, and/or stimulus signals to the IP block to facilitate circuit-level testing of the IP block. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: July 29, 2014
    Assignee: Intel Corporation
    Inventors: Srinivas Patil, Abhijit Jas, Peter Lisherness, Enrico Carrieri
  • Publication number: 20130268808
    Abstract: A Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to the Test Wrappers via an interconnect fabric. The Test Wrappers employ one or more test ports to provide test data, control, and/or stimulus signals to the IP block to facilitate circuit-level testing of the IP block. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric.
    Type: Application
    Filed: June 5, 2013
    Publication date: October 10, 2013
    Inventors: Srinivas Patil, Abhijit Jas
  • Patent number: 8522189
    Abstract: A Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to the Test Wrappers via an interconnect fabric. The Test Wrappers employ one or more test ports to provide test data, control, and/or stimulus signals to the IP block to facilitate circuit-level testing of the IP block. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: August 27, 2013
    Assignee: Intel Corporation
    Inventors: Srinivas Patil, Abhijit Jas
  • Patent number: 8489637
    Abstract: Methods, systems, and computer program products for managing access to a Domain Name Service (DNS) database. Embodiments of the present disclosure enable authorization of DNS request messages, such as queries and update requests according to user and network address information. The authorization functionality may be incorporated into existing DNS systems. The invention includes a method including receiving a DNS request message originated from a client by a user, the DNS request message comprising a request and identification information specific to the user; determining if the client is authorized to access a DNS database in dependence upon client address information and the user specific identification information contained in the DNS request message; and executing the request in response to determining the user is authorized. The method may further include extracting user specific identification information from a portion of the ID field of DNS messages.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: July 16, 2013
    Assignee: International Business Machines Corporation
    Inventor: Poornima Srinivas Patil
  • Patent number: 8424106
    Abstract: A method, system, and computer usable program product for securing a data communication against attacks are provided in the illustrative embodiments. A segment in the data communication is received at a first application executing in a first data processing system. The segment is formed according to a data communication protocol and includes an option. The option includes a current clue and a next clue. The current clue is compared with a saved next clue, the saved next clue being a next clue in a previous segment. The segment is accepted as being a valid segment in the data communication if the current clue matches the saved next clue. A part of the segment is sent to a consumer application.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: April 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: David Richard Marquardt, Prashant Anant Paranjape, Poornima Srinivas Patil
  • Publication number: 20120232825
    Abstract: A Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to the Test Wrappers via an interconnect fabric. The Test Wrappers employ interface with one or more test ports to provide test data, control, and/or stimulus signals to the IP block to facilitate circuit-level testing of the IP block. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric.
    Type: Application
    Filed: March 9, 2011
    Publication date: September 13, 2012
    Inventors: Srinivas Patil, Abhijit Jas, Peter Lisherness, Enrico Carrieri
  • Publication number: 20120233514
    Abstract: A Test Wrapper and associated Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to one or more Test Wrappers via an interconnect fabric. The Test Wrappers interface with one or more IP test ports to provide test data, control, and/or stimulus signals to the IP blocks to facilitate circuit-level testing of the IP blocks. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric.
    Type: Application
    Filed: March 9, 2011
    Publication date: September 13, 2012
    Inventors: Srinivas Patil, Abhijit Jas, Peter Lisherness
  • Publication number: 20120233504
    Abstract: A Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to the Test Wrappers via an interconnect fabric. The Test Wrappers employ one or more test ports to provide test data, control, and/or stimulus signals to the IP block to facilitate circuit-level testing of the IP block. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric.
    Type: Application
    Filed: March 9, 2011
    Publication date: September 13, 2012
    Inventors: Srinivas Patil, Abhijit Jas
  • Publication number: 20110283367
    Abstract: A method, system, and computer usable program product for securing a data communication against attacks are provided in the illustrative embodiments. A segment in the data communication is received at a first application executing in a first data processing system. The segment is formed according to a data communication protocol and includes an option. The option includes a current clue and a next clue. The current clue is compared with a saved next clue, the saved next clue being a next clue in a previous segment. The segment is accepted as being a valid segment in the data communication if the current clue matches the saved next clue. A part of the segment is sent to a consumer application.
    Type: Application
    Filed: May 13, 2010
    Publication date: November 17, 2011
    Applicant: International Business Machines Corporation
    Inventors: David Richard Marquardt, Prashant Anant Paranjape, Poornima Srinivas Patil
  • Patent number: 7861116
    Abstract: A method, apparatus and system for accepting a plurality of user-selected properties pre-designated for detecting errors in portions of a circuit, accepting a plurality of user-selected erroneous outputs, each of which may correspond to one of the plurality of user-selected set of properties, executing a simulation of the circuit for each of the plurality of user-selected properties, detecting in the output of the simulation, one of the plurality of user-selected erroneous outputs of the circuit for the corresponding one of the plurality of user-selected properties, and performing error correction on the circuit for the corresponding one of the plurality of user-selected properties. A method, apparatus and system for automatically selecting a subset of a set of inputs which when input into a circuit simulation generate erroneous output data to a primary output of the circuit and performing error correction on the circuit therewith. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: December 28, 2010
    Assignee: Intel Corporation
    Inventors: Abhijit Jas, Srinivas Patil, Rajesh Galivanche, Ramtilak Vemu
  • Publication number: 20090172529
    Abstract: A method, apparatus and system for accepting a plurality of user-selected properties pre-designated for detecting errors in portions of a circuit, accepting a plurality of user-selected erroneous outputs, each of which may correspond to one of the plurality of user-selected set of properties, executing a simulation of the circuit for each of the plurality of user-selected properties, detecting in the output of the simulation, one of the plurality of user-selected erroneous outputs of the circuit for the corresponding one of the plurality of user-selected properties, and performing error correction on the circuit for the corresponding one of the plurality of user-selected properties. A method, apparatus and system for automatically selecting a subset of a set of inputs which when input into a circuit simulation generate erroneous output data to a primary output of the circuit and performing error correction on the circuit therewith. Other embodiments are described and claimed.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Inventors: Abhijit Jas, Srinivas Patil, Rajesh Galivanche, Ramtilak Vemu
  • Publication number: 20070168767
    Abstract: A testing architecture for testing a complex integrated circuit in which each functional unit may be tested independently of the others. Embodiments of the invention allow testing of functional units to take place at slower or faster clock speeds than other portions of the processor without incurring delay or other adverse timing effects.
    Type: Application
    Filed: September 12, 2006
    Publication date: July 19, 2007
    Inventors: Talal Jaber, Srinivas Patil, Larry Thatcher, Chih-Jen Lin, Anil Sabbavarapu, David Wu, Madhukar Reddy
  • Patent number: 7216274
    Abstract: A testing architecture for testing a complex integrated circuit in which each functional unit may be tested independently of the others. Embodiments of the invention allow testing of functional units to take place at slower or faster clock speeds than other portions of the processor without incurring delay or other adverse timing effects.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: May 8, 2007
    Assignee: Intel Corporation
    Inventors: Talal K. Jaber, Srinivas Patil, Larry E. Thatcher, Chih-Jen M. Lin, Anil K. Sabbavarapu, David M. Wu, Madhukar K. Reddy
  • Patent number: 7197721
    Abstract: According to some embodiments, provided are a pseudo-random sequence generator to generate a pseudo-random sequence of data values, a decoder to receive compressed weight values and to generate decompressed weight values, and a weighting unit to receive the pseudo-random sequence of data values, to receive the decompressed weight values and to weight the pseudo-random sequence of data values based on the decompressed weight values.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: March 27, 2007
    Assignee: Intel Corporation
    Inventors: Srinivas Patil, Sandip Kundu
  • Patent number: 7155648
    Abstract: An apparatus has an integrated circuit that includes a seed register, a linear feedback shift register to load a test vector into a number of scan chains, and a signature register to receive a test response from the scan chains. The seed register, the linear feedback shift register, and the signature register each have the same register length. The linear feedback shift register and the signature register have the same shift frequency that is greater than a frequency at which a seed vector is loaded into the seed register. The linear feedback shift register is adapted to be selectively provided with bits to control a degree to which its vector is dependent on previous vectors. The scan chains may be configured as a single group providing a test response to a single input signature register or a set of groups providing a test response to a multiple input signature register.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: December 26, 2006
    Assignee: Intel Corporation
    Inventors: Abhijit Jas, Srinivas Patil
  • Publication number: 20050066244
    Abstract: An apparatus has an integrated circuit that includes a seed register, a linear feedback shift register to load a test vector into a number of scan chains, and a signature register to receive a test response from the scan chains. The seed register, the linear feedback shift register, and the signature register each have the same register length. The linear feedback shift register and the signature register have the same shift frequency that is greater than a frequency at which a seed vector is loaded into the seed register. The linear feedback shift register is adapted to be selectively provided with bits to control a degree to which its vector is dependent on previous vectors. The scan chains may be configured as a single group providing a test response to a single input signature register or a set of groups providing a test response to a multiple input signature register.
    Type: Application
    Filed: September 19, 2003
    Publication date: March 24, 2005
    Inventors: Abhijit Jas, Srinivas Patil