Abstract: The present invention disclosed an ultra-high strength steel for structural components, a process of making such steel that has a desirable microstructure in the thermo-mechanically processed and differently cooled conditions that delivers high fatigue performance in service, and a process of making forged components using such steel. The steel and the process of its manufacturing enables manufacture of components that exhibit bainitic microstructure that impart ultra-high strength ranges with very high fatigue performance. The invention enables saving in alloying additives compared to hardened and tempered alloy steels and in addition avoid expensive heat treatment operations to achieve the desired range of mechanical properties. The steel of the invention is a suitable replacement for micro alloyed steel or heat treated steel bars used for structural component development.

Abstract: In general, techniques are described for allocating virtual output queue (VOQ) buffer space to ingress forwarding units of a network device based on drain rates at which network packets are forwarded from VOQs of the ingress forwarding units. For example, a network device includes multiple ingress forwarding units that each forward network packets to an output queue of an egress forwarding unit. Ingress forwarding units each include a VOQ that corresponds to the output queue. The drain rate at any particular ingress forwarding unit corresponds to its share of bandwidth to the output queue, as determined by the egress forwarding unit. Each ingress forwarding unit configures its VOQ buffer size in proportion to its respective drain rate in order to provide an expected delay bandwidth buffering for the output queue of the egress forwarding unit.

Abstract: A device may receive a request to read data from or write data to a memory that includes a number of memory banks. The request may include an address. The device may perform a mapping operation on the address to map the address from a first address space to a second address space, identify one of the memory banks based on the address in the second address space, and send the request to the identified memory bank.

Abstract: A device may receive a request to read data from or write data to a memory that includes a number of memory banks. The request may include an address. The device may perform a mapping operation on the address to map the address from a first address space to a second address space, identify one of the memory banks based on the address in the second address space, and send the request to the identified memory bank.

Abstract: A device may receive requests intended for a memory that includes a number of banks, determine a number of the requests intended for each of the banks, determine an order for the requests based on the determined number of the requests intended for each of the banks, and send one of the requests to the memory based on the determined order.

Abstract: A device includes a memory that includes a number of banks. The device receives requests for accessing the memory, determines the banks to which the requests are intended, determines one or more of the banks that are available, selects one or more of the requests to send to the memory based on the one or more of the banks that are available and have a request to be serviced, and sends the selected one or more requests to the memory.

Abstract: A device may include a group of requestors issuing requests, a memory that includes a set of memory banks, and a control block. The control block may receive a request from one of the requestors, where the request includes a first address. The control block may perform a logic operation on a high order bit and a low order bit of the first address to form a second address, identify one of the memory banks based on the second address, and send the request to the identified memory bank.

Abstract: A lifetime-based memory management scheme is described, whereby a network device first determines an expected lifetime for received packets, which correlates to the expected output queue latency time of the packets. The network device then buffers packets having matching lifetimes to memory pages dedicated to that lifetime.

Abstract: A device may generate a refresh signal that identifies a beginning of a refresh interval, determine the availability of banks of a memory device, and send refresh requests to the banks during the refresh interval based on the availability of the banks.

Abstract: A device may include a group of requestors issuing requests, a memory that includes a set of memory banks, and a control block. The control block may receive a request from one of the requestors, where the request includes a first address. The control block may perform a logic operation on a high order bit and a low order bit of the first address to form a second address, identify one of the memory banks based on the second address, and send the request to the identified memory bank.

Abstract: A device may include a group of requestors issuing requests, a memory that includes a set of memory banks, and a control block. The control block may receive a request from one of the requestors, where the request includes a first address. The control block may perform a logic operation on a high order bit and a low order bit of the first address to form a second address, identify one of the memory banks based on the second address, and send the request to the identified memory bank.