Patents by Inventor Srinivas Pietambaram

Srinivas Pietambaram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200312771
    Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 1, 2020
    Inventors: Bai NIE, Gang DUAN, Srinivas PIETAMBARAM, Jesse JONES, Yosuke KANAOKA, Hongxia FENG, Dingying XU, Rahul MANEPALLI, Sameer PAITAL, Kristof DARMAWIKARTA, Yonggang LI, Meizi JIAO, Chong ZHANG, Matthew TINGEY, Jung Kyu HAN, Haobo CHEN
  • Publication number: 20200312768
    Abstract: An interconnection structure is disclosed. The interconnection structure includes a dielectric layer, an interfacial TiC layer on the dielectric layer, the interfacial TiC layer having a uniform thickness, and a Ti layer on the TiC layer.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 1, 2020
    Inventors: Suddhasattwa NAD, Rahul MANEPALLI, Srinivas PIETAMBARAM, Marcel WALL
  • Patent number: 10777514
    Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connectors can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Yikang Deng, Kyu Oh Lee, Ji Yong Park, Srinivas Pietambaram, Ying Wang, Chong Zhang, Rui Zhang, Junnan Zhao
  • Publication number: 20200266184
    Abstract: Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.
    Type: Application
    Filed: December 29, 2017
    Publication date: August 20, 2020
    Inventors: Srinivas PIETAMBARAM, Robert Alan MAY, Kristof DARMAWIKARTA, Hiroki TANAKA, Rahul N. MANEPALLI, Sri Ranga Sai BOYAPATI
  • Publication number: 20200258975
    Abstract: Embodiments disclosed herein include electronic packages with embedded magnetic materials and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of dielectric layers. In an embodiment a plurality of passive components is located in a first dielectric layer of the plurality of dielectric layers. In an embodiment, first passive components of the plurality of passive components each comprise a first magnetic material, and second passive components of the plurality of passive components each comprise a second magnetic material. In an embodiment, a composition of the first magnetic material is different than a composition of the second magnetic material.
    Type: Application
    Filed: February 8, 2019
    Publication date: August 13, 2020
    Inventors: Rengarajan SHANMUGAM, Suddhasattwa NAD, Darko GRUJICIC, Srinivas PIETAMBARAM
  • Publication number: 20200258847
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.
    Type: Application
    Filed: February 12, 2019
    Publication date: August 13, 2020
    Inventors: Srinivas PIETAMBARAM, Gang DUAN, Deepak KULKARNI, Rahul MANEPALLI, Xiaoying GUO
  • Patent number: 10705293
    Abstract: This document discusses, among other things, a waveguide including a first metal having an outer surface proximate a dielectric material and an inner surface defining a path of the waveguide, a method of receiving an optical signal at the inner surface of the waveguide and transmitting the optical signal along at least a portion of the path of the waveguide. A method of integrating a waveguide in a substrate includes depositing sacrificial metal on a first surface of a carrier substrate to form a core of the waveguide, depositing a first metal over the sacrificial metal and at least a portion of the first surface of the carrier substrate, forming an outer surface of the waveguide and a conductor separate from the sacrificial metal, and depositing dielectric material over the first surface of the carrier substrate about the conductor.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Robert Alan May, Kristof Darmawikarta, Rahul Jain, Sri Ranga Sai Boyapati, Maroun Moussallem, Rahul N. Manepalli, Srinivas Pietambaram
  • Publication number: 20200211952
    Abstract: According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height.
    Type: Application
    Filed: March 10, 2020
    Publication date: July 2, 2020
    Inventors: Rahul N. Manepalli, Kousik Ganesan, Marcel Arlan Wall, Srinivas Pietambaram
  • Patent number: 10672695
    Abstract: This document discusses, among other things, a multi-layer molded substrate having layers with a graded coefficients of thermal expansions (CTEs) to optimize thermal performance of the multi-layer molded substrate with first and second structures attached to top and bottom surfaces of the multi-layer molded substrate, respectively.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Srinivas Pietambaram, Rahul N. Manepalli
  • Patent number: 10658281
    Abstract: According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Rahul N. Manepalli, Kousik Ganesan, Marcel Arlan Wall, Srinivas Pietambaram
  • Publication number: 20200135679
    Abstract: Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).
    Type: Application
    Filed: October 31, 2018
    Publication date: April 30, 2020
    Inventors: Kristof DARMAWAIKARTA, Robert MAY, Sashi KANDANUR, Sri Ranga Sai BOYAPATI, Srinivas PIETAMBARAM, Steve CHO, Jung Kyu HAN, Thomas HEATON, Ali LEHAF, Ravindranadh ELURI, Hiroki TANAKA, Aleksandar ALEKSOV, Dilan SENEVIRATNE
  • Publication number: 20200083164
    Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.
    Type: Application
    Filed: September 12, 2018
    Publication date: March 12, 2020
    Inventors: Brandon C. MARIN, Frank TRUONG, Shivasubramanian BALASUBRAMANIAN, Dilan SENEVIRATNE, Yonggang LI, Sameer PAITAL, Darko GRUJICIC, Rengarajan SHANMUGAM, Melissa WETTE, Srinivas PIETAMBARAM
  • Publication number: 20200005987
    Abstract: Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of electrically conductive elements. The magnetic foil can be positioned to interface with and be spaced from the one or more of electrically conductive element.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Srinivas Pietambaram, Kristof Darmawikarta, Gang Duan, Yonggang Li, Sameer Paital
  • Publication number: 20200006232
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Srinivas PIETAMBARAM, Rahul MANEPALLI, Gang DUAN
  • Publication number: 20200005990
    Abstract: Embodiments herein relate to systems, apparatuses, or processes for embedding a magnetic core or a magnetic inductor in a substrate layer by applying a copper layer to a portion of the substrate layer, creating a structure in the substrate layer on top of at least part of the copper layer to identify a defined region within the substrate layer, and inserting a magnetic paste into the defined region where the copper layer identifies a side of the defined region and where the structure is to contain the magnetic paste within the defined region while the magnetic paste cures.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Sameer PAITAL, Srinivas PIETAMBARAM, Yonggang LI, Bai NIE, Kristof DARMAWIKARTA, Gang DUAN
  • Publication number: 20190385780
    Abstract: Techniques are provided for an inductor at a first level interface between a first die and a second die. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first die, second conductive traces of a second die, and a plurality of connectors configured to connect the first die with the second die. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.
    Type: Application
    Filed: June 19, 2018
    Publication date: December 19, 2019
    Inventors: Cheng Xu, Yikang Deng, Kyu Oh Lee, Ji Yong Park, Srinivas Pietambaram, Ying Wang, Chong Zhang, Rui Zhang, Junnan Zhao
  • Publication number: 20190385959
    Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.
    Type: Application
    Filed: June 19, 2018
    Publication date: December 19, 2019
    Inventors: Cheng Xu, Yikang Deng, Kyu Oh Lee, Ji Yong Park, Srinivas Pietambaram, Ying Wang, Chong Zhang, Rui Zhang, Junnan Zhao
  • Publication number: 20190355647
    Abstract: Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.
    Type: Application
    Filed: July 31, 2019
    Publication date: November 21, 2019
    Inventors: Aleksandar ALEKSOV, Hiroki TANAKA, Robert A. MAY, Kristof DARMAWIKARTA, Changhua LIU, Chung Kwang TAN, Srinivas PIETAMBARAM, Sri Ranga Sai BOYAPATI
  • Publication number: 20190312019
    Abstract: Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die.
    Type: Application
    Filed: April 10, 2018
    Publication date: October 10, 2019
    Inventors: Srinivas Pietambaram, Gang Duan, Deepak Kulkarni
  • Patent number: 10431537
    Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: October 1, 2019
    Assignee: Intel Corporation
    Inventors: Srinivas Pietambaram, Jung Kyu Han, Ali Lehaf, Steve Cho, Thomas Heaton, Hiroki Tanaka, Kristof Darmawikarta, Robert Alan May, Sri Ranga Sai Boyapati