Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

Abstract: The present disclosure is directed to semiconductor dies and methods that provide a glass substrate, a pulsed laser tool to produce a line-shaped modification to the glass substrate for forming a plurality of structures in the glass substrate. The pulse laser tool may be provided with a predetermined pattern for its movement. The predetermined pattern moves the pulsed laser tool in a series of single steps in a first axial direction and in a series of plural lateral steps in a second axial direction that is perpendicular to the first axial direction, in particular, the single step is followed by the plural lateral steps in a repeating sequence. The series of plural lateral steps form an assembly of line-shaped modifications in parallel rows on the glass substrate, and thereafter the plurality of structures may be formed from the parallel rows of line-shaped modifications in the glass substrate.

Abstract: An apparatus is provided which comprises: a substrate core comprising a first core layer and a second core layer, one or more redistribution layers on a first substrate core surface, one or more conductive contacts on a second substrate core surface opposite the first substrate core surface, one or more vias through the substrate core, a first circuit component embedded entirely within a cavity in the first core layer, the first circuit component coupled with a first redistribution layers surface, wherein the first circuit component and the first core layer have substantially equivalent heights, and a second circuit component embedded entirely within a cavity in the second core layer, wherein the second circuit component and the second core layer have substantially equivalent heights. Other embodiments are also disclosed and claimed.

Abstract: An apparatus includes a substrate, a cavity within the substrate, and a die within the cavity. The substrate has an exterior surface. The cavity includes a first surface and a second surface opposite the first surface. The die includes a discrete component, a first side, a second side opposite the first side, and conductive features at the first side. In an embodiment, a bond film is between the first surface and the first side. A plurality of conductive vias extend from the exterior surface through the substrate and bond film to the conductive features. In an embodiment, the bond film may be omitted. The plurality of conductive vias extend from the exterior surface through the substrate. The conductive features of the die are coupled with the conductive vias by solder features, and the second side of the die is spaced away from the second surface.

Abstract: Example methods and apparatus for embedding interconnect bridges having through silicon vias in substrates are disclosed. An example semiconductor package a bridge die disposed in a recess of an underlying substrate, the bridge die including a via that electrically couples a first contact on a first side of the bridge die and a second contact on a second side of the bridge die, the recess extending to a first surface of the underlying substrate; a bond material to electrically and mechanically couple the first contact and an interconnect of the underlying substrate; and a fill material positioned between the first side of the bridge die and the first surface of the underlying substrate.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to embed a semiconductor device in a glass core. An example apparatus comprises a package substrate comprising a glass core having a cavity in an outer surface of the glass core, the outer surface defining a first plane, and a semiconductor die attached to a surface of the cavity, the semiconductor die having contact pads on a surface of the semiconductor die, the contact pads arranged in a second plane, the second plane substantially coplanar with the first plane.

Abstract: Semiconductor chip package substrates having interconnect bridges, assemblies including these semiconductor chip package substrates, and methods of manufacturing interconnect-bridge-containing semiconductor package chip substrates are provided. The interconnect bridges can include through-bridge vias that are electrically coupled to the semiconductor package substrate. The embedded bridges can be aligned to fiducials within the semiconductor package substrate.

Abstract: Methods and apparatus for mounting semiconductor devices in cavities are disclosed herein. An example semiconductor package includes a package substrate core having a cavity positioned therein; a pedestal positioned within the cavity of the core, the pedestal including a conductive material; and a capacitor disposed within the cavity, the capacitor positioned on the pedestal.

Abstract: An apparatus includes a substrate core, which has a first height between a first surface and a second surface opposite the first surface. A die is within the substrate core. The die may include a deep trench capacitor. The die has a second height between a first side of the die and a second side opposite the first side. The first height is greater than the second height. A plurality of conductive vias extend from a plurality of conductive contacts at the first side of the die to the first surface of the substrate core. A material comprising a dielectric is disposed over the die and encapsulates the plurality of conductive vias. In some embodiments, a bond film is in contact with the second side of the die.

Abstract: Assemblies that include package substrates and semiconductor chips are provided. The package substrates include interconnect bridges having through-bridge vias. The assemblies also include alignment features and receiving cavities.

Abstract: Microelectronic integrated circuit package structures include an apparatus having a a glass substrate embedded within a package substrate. The glass substrate comprises one or more trenches extending within a first portion, the one or more trenches comprising a first conductive layer on individual trench sidewalls, a dielectric layer on the first conductive layer and a second conductive layer on the dielectric layer. A second portion of the glass substrate is below the first portion.

Abstract: Microelectronic integrated circuit package structures include one or more trench capacitors extending through a portion a device structure. The device structure is embedded within a portion of a core layer of a multi core package substrate, wherein one or more conductive interconnect structures are coupled with the one or more trench capacitors. A thickness of the device structure is equal to a thickness of the core layer.

Abstract: An apparatus comprises a substrate core comprising a hole extending from an opening at a first surface of the substrate core to a second surface opposite the first surface. A metal layer is over the first surface. The metal layer comprises a plurality of first metal features over a first portion of the opening. The metal layer also includes a second metal feature extending from a sidewall of the hole and over a second portion of the opening. A die is within the hole and coupled to the first metal features by solder features. The die may comprise a capacitor.

Abstract: An apparatus is provided which comprises: a substrate core comprising a first core layer bonded with a second core layer, one or more redistribution layers on a first substrate core surface, one or more conductive contacts on a second substrate core surface opposite the first substrate core surface, one or more vias through the substrate core, a first circuit component embedded entirely within a cavity in the first core layer, the first circuit component coupled with a first redistribution layers surface, wherein the first circuit component and the first core layer have substantially equivalent heights, and wherein the first circuit component comprises a deep trench capacitor, and one or more integrated circuit devices coupled with a second redistribution layers surface opposite the first redistribution layers surface. Other embodiments are also disclosed and claimed.

Abstract: Assemblies and methods of manufacturing assemblies comprising semiconductor chips and package substrates wherein the semiconductor chips are operably coupled to the package substrate through a solderless direct metal-to-metal bond region. The solderless direct metal-to-metal bond region also comprises a dielectric polymer. Package substrates can comprise interconnect bridges and the semiconductor chips can be operably coupled to the interconnect bridges and can also be operably coupled to each other through the interconnect bridges.

Abstract: Processes and process equipment for modifying edges of semiconductor package substrates, and semiconductor package substrates having modified edges are provided. The processes and process equipment are especially useful for semiconductor package substrates that have cores that can crack or chip during processing, such as, for example, cores comprised of glass. Semiconductor package substrates having glass cores and modified edges are also provided.

Abstract: Apparatuses, capacitor structures, systems, and techniques related to capacitors having passivation boundary defects within a polycrystalline dielectric material of the capacitor are discussed. The polycrystalline dielectric material includes crystalline grains of a first composition having grain boundaries between the crystalline grains. At some of the grain boundaries, the polycrystalline dielectric material includes amorphous passivation material having a second composition.

Abstract: Apparatuses, capacitor modules, assemblies, and techniques related to package substrate embedded capacitors are described. A capacitor module is formed by fabricating capacitor structures along a surface of one or more substrates, cutting the capacitor structures from the one or more substrates and stacking the resultant capacitor structures and substrates into a capacitor module. The capacitor module is then vertically embedded in a package substrate or core.

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

Abstract: An integrated circuit (IC) package substrate, comprising a magnetic material embedded within a dielectric material. A first surface of the dielectric material is below the magnetic material, and a second surface of the dielectric material, opposite the first surface, is over the magnetic material. A metallization level comprising a first metal feature is embedded within the magnetic material. A second metal feature is at an interface of the magnetic material and the dielectric material. The second metal feature has a first sidewall in contact with the dielectric material and a second sidewall in contact with the magnetic material.