Abstract: Optimizing compositor workload in steady state in processor devices is disclosed herein. In some aspects, a processor device is configured to perform image compositing by executing a compositor pipeline that comprises a compositor including a workload handler; a composer Hardware Abstraction Layer (HAL); a workload governor communicatively coupled to the composer HAL; and a display driver. The workload governor detects that the image compositing has entered a steady state, and transmits an indication to enter an accelerated mode to the workload handler. Upon receiving the indication, the workload handler places the compositor pipeline in the accelerated mode. While in the accelerated mode, the compositor transmits accelerated mode data directly to the display driver, bypassing the composer HAL.

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for DPU driven adaptive synchronization for command mode displays. A display processor may obtain one or more frame content buffers for a frame composition cycle. The display processor may obtain a fence for the one or more frame content buffers. The display processor may receive a signal for the fence for the one or more frame content buffers. The display processor may compose a first frame associated with the one or more frame content buffers for the frame composition cycle. The display processor may transfer, to a display memory of a display, data for the first frame associated with a first synchronization signal. The data for the first frame may be transferred at a default transfer rate or a boosted transfer rate.

Abstract: Aspects of the disclosure are directed to implementing adaptive variable refresh (AVR) wherein a graphics processing unit (GPU) is configured to generate a display content; a display processing unit (DPU) coupled to the graphics processing unit (GPU), wherein the DPU is configured to provide an adaptive variable refresh (AVR) feature; and a display panel coupled to the DPU, wherein the display panel is configured to display the display content.

Abstract: Aspects presented herein relate to methods and devices for display processing including an apparatus, e.g., a CPU. The apparatus may perform a partial frame update for a first frame at a first update time, where the partial frame update corresponds to an update of less than all content in the first frame, where the partial frame update for the first frame is associated with a panel ROI of the first frame. The apparatus may also calculate a margin time period between the first update time and a subsequent Vsync time. Further, the apparatus may transmit, based on the margin time period, a first indication of a subsequent frame transfer interrupt time. The apparatus may also transmit, to a DPU, a second indication to transfer the set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency starting at the subsequent frame transfer interrupt time.

Abstract: Methods, systems, and devices for adaptive display data transfer rate to reduce power consumption during partial frame composition are described. The method may include identifying a set of frames for display on a panel of the device, determining a starting line of an updating frame region of the set of frames in relation to a first pixel line of the panel, determining an ending line of the updating frame region of the set of frames in relation to the first pixel line of the panel, reducing a bus bandwidth vote based on the starting line of the updating frame region, or the ending line of the updating frame region, or a number of lines of the updating frame region, or any combination thereof, and transferring the lines of the updating frame region from a display processor unit to a panel memory at the reduced bus bandwidth.

Abstract: The present disclosure relates to methods and apparatus for display processing. The apparatus can determine at least one data parameter corresponding to each of a plurality of layers in a display frame. The apparatus can also calculate a model for the at least one data parameter corresponding to each of the plurality of layers. Additionally, the apparatus can modify the model for the at least one data parameter based on one or more application use cases of the display frame. Moreover, the apparatus can implement the modified model on each of the plurality of layers in the display frame. In some aspects, the apparatus can also determine one or more composition settings for each of the plurality of layers based on the modified model. The apparatus can also apply the one or more composition settings to each of the plurality of layers based on the modified model.

Abstract: The present disclosure relates to methods and apparatus for display processing. The apparatus can receive a first frame at a frame ready time associated with a current vertical synchronization (Vsync) time period including a first Vsync time and a second Vsync time, the frame ready time may be between the first Vsync time and the second Vsync time, the current Vsync time period may be distinct from one or more application Vsync time periods. The apparatus can also determine one of the one or more application Vsync time periods to align with the current Vsync time period based on the frame ready time. Moreover, the apparatus can adjust an alignment of the current Vsync time period to align with the one of the one or more application Vsync time periods. The apparatus can also adjust the second Vsync time to align the current Vsync time period.

Abstract: In some aspects, the present disclosure provides a method for generating a frame. The method includes receiving a first fence indicating that a first frame stored in a display processor unit (DPU) buffer has been consumed by a hardware component. The method also includes in response to receiving the first fence, fetching a plurality of layers from an application buffer, the plurality of layers corresponding to a second frame. The method also includes determining to use both a DPU and a graphics processing unit (GPU) to process the plurality of layers for composition of the second frame. The method also includes fetching the first fence from the DPU buffer and generating a second fence.

Abstract: The present disclosure relates to methods and apparatus for display processing. The apparatus can monitor a rendering time for each of a plurality of layers in a display frame. The apparatus can also determine whether a rendering time of one or more layers is greater than a maximum rendering time threshold. The apparatus can also adjust a rendering resolution of the one or more layers when the rendering time of the one or more layers is greater than the maximum rendering time threshold. Moreover, the apparatus can reduce the rendering resolution of the one or more layers when the rendering time of the one or more layers is greater than the maximum rendering time threshold. Also, the apparatus can increase the rendering resolution of the one or more layers when the rendering time of the one or more layers is less than a minimum rendering time threshold.

Abstract: The present disclosure relates to methods and apparatus for display processing. Aspects of the present disclosure can determine a refresh offset for at least one group of lines in a first display based on at least one group of lines in a second display. Aspects of the present disclosure can also apply the refresh offset for the at least one group of lines in the first display based on the at least one group of lines in the second display. Further, aspects of the present disclosure can adjust combined instantaneous bandwidth corresponding to each of the at least one group of lines in the first display and each of the at least one group of lines in the second display based on the applied refresh offset. Aspects of the present disclosure can also determine one or more overlapping layer regions based on the first display and the second display.

Abstract: The present disclosure relates to methods and apparatus for display processing. The apparatus can determine at least one data parameter corresponding to each of a plurality of layers in a display frame. The apparatus can also calculate a model for the at least one data parameter corresponding to each of the plurality of layers. Additionally, the apparatus can modify the model for the at least one data parameter based on one or more application use cases of the display frame. Moreover, the apparatus can implement the modified model on each of the plurality of layers in the display frame. In some aspects, the apparatus can also determine one or more composition settings for each of the plurality of layers based on the modified model. The apparatus can also apply the one or more composition settings to each of the plurality of layers based on the modified model.

Abstract: The present disclosure relates to methods and apparatus for display processing. Aspects of the present disclosure can determine a refresh offset for at least one group of lines in a first display based on at least one group of lines in a second display. Aspects of the present disclosure can also apply the refresh offset for the at least one group of lines in the first display based on the at least one group of lines in the second display. Further, aspects of the present disclosure can adjust combined instantaneous bandwidth corresponding to each of the at least one group of lines in the first display and each of the at least one group of lines in the second display based on the applied refresh offset. Aspects of the present disclosure can also determine one or more overlapping layer regions based on the first display and the second display.

Abstract: Certain aspects of the present disclosure provide a method for driving a plurality of display panels including a first display panel and a second display panel. The method includes receiving a first synchronization signal from the first display panel. The method further includes receiving a second synchronization signal from the second display panel. The method further includes determining a phase difference between the first synchronization signal and the second synchronization signal. The method further includes computing at least one phase shift offset based on the determined phase difference, the at least one phase shift offset being configured to reduce the phase difference between the first synchronization signal and the second synchronization signal. The method further includes providing a first phase shift offset of the at least one phase shift offset to the first display panel. The method further includes providing a unified synchronization signal to a display processor.

Abstract: Certain aspects of the present disclosure provide a method for driving a plurality of display panels including a first display panel and a second display panel. The method includes receiving a first synchronization signal from the first display panel. The method further includes receiving a second synchronization signal from the second display panel. The method further includes determining a phase difference between the first synchronization signal and the second synchronization signal. The method further includes computing at least one phase shift offset based on the determined phase difference, the at least one phase shift offset being configured to reduce the phase difference between the first synchronization signal and the second synchronization signal. The method further includes providing a first phase shift offset of the at least one phase shift offset to the first display panel. The method further includes providing a unified synchronization signal to a display processor.

Abstract: A display panel of a device may receive, from a host processor of the device, an inline pixel operation instruction comprising an indication of a first linear adjustment for a set of source pixel values for a display region of the display. The display panel may generate a pixel pattern for the display region by applying the first linear adjustment to the set of source pixel values and display the pixel pattern on the display. The display panel may in some cases read the set of source pixel values from a frame buffer of the device. The display panel may in some cases determine a color component tuple for each pixel of the display region based at least in part on the indication of the first linear adjustment, wherein the pixel pattern for the display region is based at least in part on the color component tuple.

Abstract: A device may allocate one or more frame buffers. In response to a command to open an application after allocating the one or more frame buffers, the device may reassign one or more of the frame buffers to the application. Furthermore, the device may store, based on instructions of the application, content data in the one or more reassigned frame buffers. The device may output, for display on a display screen, content based on the content data in the one or more reassigned frame buffers.

Abstract: A device may allocate one or more frame buffers. In response to a command to open an application after allocating the one or more frame buffers, the device may reassign one or more of the frame buffers to the application. Furthermore, the device may store, based on instructions of the application, content data in the one or more reassigned frame buffers. The device may output, for display on a display screen, content based on the content data in the one or more reassigned frame buffers.

Abstract: A method and system for displaying image data on a video-mode display panel is provided. Instead of continuously refreshing the entire display panel, the display panel may be divided into a first frame region and a second frame region. Each frame region may be associated with its own refresh rate. A higher refresh rate can be provided to content such as video playback and scrolling where a higher refresh rate is required for improved user experience and reduce visual artifacts. A lower refresh rate can be provided to other content, thus saving power where higher refresh rate is not required.