Patents by Inventor Srinivas Pulugurtha

Srinivas Pulugurtha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250240951
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line.
    Type: Application
    Filed: January 16, 2025
    Publication date: July 24, 2025
    Inventors: Srinivas Pulugurtha, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20250126773
    Abstract: Some embodiments include apparatuses and methods using the apparatuses. One of the embodiments includes a capacitor, a transistor coupled to the capacitor, the transistor and the capacitor included in a memory cell; the transistor including a channel structure, a gate including a portion located on a side of the channel structure, and a dielectric structure between the channel structure and the gate; and on-die circuitry configured to selectively apply a stress condition to the transistor to tune a threshold voltage of the transistor.
    Type: Application
    Filed: December 23, 2024
    Publication date: April 17, 2025
    Inventors: Anthony J. Kanago, Jaydip Guha, Srinivas Pulugurtha, Soichi Sugiura
  • Patent number: 12279445
    Abstract: A semiconductor structure includes a semiconductor substrate containing a shallow trench isolation structure that laterally surrounds a transistor active region, at least one line trench vertically extending into the semiconductor substrate, and a source region and a drain region located in the transistor active region. A contoured channel region continuously extends from the source region to the drain region underneath the at least one line trench. A gate dielectric contacts all surfaces of the at least one line trench and extends over an entirety of the contoured channel region. A gate electrode containing at least one fin portion overlies the gate dielectric.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: April 15, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Srinivas Pulugurtha, Yanli Zhang, Johann Alsmeier, Mitsuhiro Togo
  • Patent number: 12232311
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line.
    Type: Grant
    Filed: November 10, 2023
    Date of Patent: February 18, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Srinivas Pulugurtha, Durai Vishak Nirmal Ramaswamy
  • Patent number: 12178033
    Abstract: Some embodiments include apparatuses and methods using the apparatuses. One of the embodiments includes a capacitor, a transistor coupled to the capacitor, the transistor and the capacitor included in a memory cell; the transistor including a channel structure, a gate including a portion located on a side of the channel structure, and a dielectric structure between the channel structure and the gate; and on-die circuitry configured to selectively apply a stress condition to the transistor to tune a threshold voltage of the transistor.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: December 24, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Anthony J. Kanago, Jaydip Guha, Srinivas Pulugurtha, Soichi Sugiura
  • Publication number: 20240381628
    Abstract: A variety of applications can include a memory device having a memory array region on a memory die and a periphery to the memory array region on the memory die, where the periphery can include a fully depleted silicon-on-insulator (FDSOI) complementary metal-oxide-semiconductor (CMOS) device. A metal shield can be integrated in the memory array region, where the metal shield is structured as a shield to digit lines of the memory array. A metal body plate in the periphery can be structured as a back gate to the FDSOI CMOS device.
    Type: Application
    Filed: May 9, 2024
    Publication date: November 14, 2024
    Inventors: Srinivas Pulugurtha, Anthony J. Kanago
  • Publication number: 20240373619
    Abstract: Some embodiments include apparatuses and methods of forming the apparatus. One of the apparatuses and methods includes a memory cell having a first transistor and a second transistor located over a substrate. The first transistor includes a channel region. The second transistor includes a channel region located over the channel region of the first transistor and electrically separated from the first channel region. The memory cell includes a memory element located on at least one side of the channel region of the first transistor. The memory element is electrically separated from the channel region of the first transistor, and electrically coupled to the channel of the second transistor.
    Type: Application
    Filed: May 13, 2024
    Publication date: November 7, 2024
    Inventors: Kamal M. Karda, Srinivas Pulugurtha, Haitao Liu, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20240284663
    Abstract: A variety of applications can include an apparatus having one or more pairs of transistors sharing a common source region that provide asymmetric transistor devices. The drains of the transistors of a pair sharing a common source region can be structured with the source junction depth being shallower than the drain junction depth of the drain region of at least one of the transistors of the pair. Tilted implantation can be used to extend a drain junction depth beyond the distance of the source junction depth by implanting additional dopants. The extension of the drain junction depth can be accomplished without additional masks being used in processing to dope only a drain region and skip doping on a corresponding source region.
    Type: Application
    Filed: February 13, 2024
    Publication date: August 22, 2024
    Inventors: Srinivas Pulugurtha, Dan Mihai Mocuta
  • Publication number: 20240196604
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line.
    Type: Application
    Filed: November 10, 2023
    Publication date: June 13, 2024
    Inventors: Srinivas Pulugurtha, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11985806
    Abstract: Some embodiments include apparatuses and methods of forming the apparatus. One of the apparatuses and methods includes a memory cell having a first transistor and a second transistor located over a substrate. The first transistor includes a channel region. The second transistor includes a channel region located over the channel region of the first transistor and electrically separated from the first channel region. The memory cell includes a memory element located on at least one side of the channel region of the first transistor. The memory element is electrically separated from the channel region of the first transistor, and electrically coupled to the channel of the second transistor.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 14, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Srinivas Pulugurtha, Haitao Liu, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11935960
    Abstract: Some embodiments include integrated memory. The integrated memory includes a first series of first conductive structures and a second series of conductive structures. The first conductive structures extend along a first direction. The second conductive structures extend along a second direction which crosses the first direction. Pillars of semiconductor material extend upwardly from the first conductive structures. Each of the pillars includes a lower source/drain region, an upper source/drain region, and a channel region between the lower and upper source/drain regions. The lower source/drain regions are coupled with the first conductive structures. Insulative material is adjacent sidewall surfaces of the pillars. The insulative material includes ZrOx, where x is a number greater than 0. The second conductive structures include gating regions which are spaced from the channel regions by at least the insulative material. Storage elements are coupled with the upper source/drain regions.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: March 19, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Srinivas Pulugurtha, Litao Yang, Haitao Liu, Kamal M. Karda
  • Patent number: 11839073
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: December 5, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Srinivas Pulugurtha, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11805649
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and at least one drain-select-level isolation structure vertically extending through at least a topmost electrically conductive layer among the electrically conductive layers. The at least one drain-select-level isolation structure may include wiggles and cut through upper portions of at least some of the memory opening fill structures, or may include a vertically-extending dielectric material portion and laterally-protruding dielectric material portions adjoined to the vertically-extending dielectric material portion and laterally protruding into lateral recesses located adjacent to the at least the topmost electrically conductive layer.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: October 31, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Srinivas Pulugurtha, Johann Alsmeier, Yanli Zhang, James Kai
  • Patent number: 11653488
    Abstract: An apparatus comprises a first conductive structure and at least one transistor in electrical communication with the first conductive structure. The at least one transistor comprises a lower conductive contact coupled to the first conductive structure and a split-body channel on the lower conductive contact. The split-body channel comprises a first semiconductive pillar and a second semiconductive pillar horizontally neighboring the first semiconductive pillar. The at least one transistor also comprises a gate structure horizontally interposed between the first semiconductive pillar and the second semiconductive pillar of the split-body channel and an upper conductive contact vertically overlying the gate structure and coupled to the split-body channel. Portions of the gate structure surround three sides of each of the first semiconductive pillar and the second semiconductive pillar. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: May 16, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Litao Yang, Srinivas Pulugurtha, Haitao Liu
  • Patent number: 11626488
    Abstract: Some embodiments include a transistor having an active region containing semiconductor material. The semiconductor material includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table. The active region has a first region, a third region offset from the first region, and a second region between the first and third regions. A gating structure is operatively adjacent to the second region. A first carrier-concentration-gradient is within the first region, and a second carrier-concentration-gradient is within the third region. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: April 11, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Srinivas Pulugurtha, Jaydip Guha, Scott E. Sills, Yi Fang Lee
  • Publication number: 20230082824
    Abstract: A semiconductor structure includes a semiconductor substrate containing a shallow trench isolation structure that laterally surrounds a transistor active region, at least one line trench vertically extending into the semiconductor substrate, and a source region and a drain region located in the transistor active region. A contoured channel region continuously extends from the source region to the drain region underneath the at least one line trench. A gate dielectric contacts all surfaces of the at least one line trench and extends over an entirety of the contoured channel region. A gate electrode containing at least one fin portion overlies the gate dielectric.
    Type: Application
    Filed: December 27, 2021
    Publication date: March 16, 2023
    Inventors: Srinivas PULUGURTHA, Yanli ZHANG, Johann ALSMEIER, Mitsuhiro TOGO
  • Patent number: 11600535
    Abstract: Some embodiments include an integrated assembly having an array of vertically-extending active regions. Each of the active regions is contained within a four-sided area. Conductive gate material is configured as first conductive structures. Each of the first conductive structures extends along a row of the array. The first conductive structures include segments along three of the four sides of each of the four-sided areas. Second conductive structures are under the active regions and extend along columns of the array. Third conductive structures extend along the rows of the array and are adjacent the fourth sides of the four-sided areas. Storage-elements are coupled with the active regions. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: March 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Litao Yang, Srinivas Pulugurtha, Yunfei Gao, Sanh D. Tang, Haitao Liu
  • Patent number: 11581317
    Abstract: Some embodiments include an integrated assembly having digit lines which extend along a first direction, and which are spaced from one another by intervening regions. Each of the intervening regions has a first width along a cross-section. Pillars extend upwardly from the digit lines; and the pillars include transistor channel regions extending vertically between upper and lower source/drain regions. Storage elements are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines are within the intervening regions and extend along the first direction. The shield lines may be coupled with at least one reference voltage node. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: February 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Srinivas Pulugurtha, Richard J. Hill, Yunfei Gao, Nicholas R. Tapias, Litao Yang, Haitao Liu
  • Patent number: 11581319
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: February 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Srinivas Pulugurtha, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20230030364
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line.
    Type: Application
    Filed: October 6, 2022
    Publication date: February 2, 2023
    Inventors: Srinivas Pulugurtha, Durai Vishak Nirmal Ramaswamy