Abstract: Embodiments include a system for performance monitoring, the system includes a processor configured to perform a method. The method includes detecting, by a redundancy register, a change to a counter value corresponding to one of a plurality of hardware counters, wherein the redundancy register comprises a plurality of memory locations; storing, in each of the plurality of memory locations, a value indicating a change was detected for the counter value corresponding to the plurality of hardware counters, wherein each of the plurality of hardware counters map to one of the plurality of memory locations; performing read operation on a subset of the hardware counters, wherein members of the subset of the hardware counters are determined based upon the value indicating that the change was detected for the counter value corresponding to the plurality of hardware counters; and resetting the value stored in all the memory locations to a default value.

Abstract: Embodiments include a system for performance monitoring, the system includes a processor configured to perform a method. The method includes detecting, by a redundancy register, a change to a counter value corresponding to one of a plurality of hardware counters, wherein the redundancy register comprises a plurality of memory locations; storing, in each of the plurality of memory locations, a value indicating a change was detected for the counter value corresponding to the plurality of hardware counters, wherein each of the plurality of hardware counters map to one of the plurality of memory locations; performing read operation on a subset of the hardware counters, wherein members of the subset of the hardware counters are determined based upon the value indicating that the change was detected for the counter value corresponding to the plurality of hardware counters; and resetting the value stored in all the memory locations to a default value.

Abstract: Embodiments include a system for performance monitoring, the system includes a processor configured to perform a method. The method includes detecting, by a redundancy register, a change to a counter value corresponding to one of a plurality of hardware counters, wherein the redundancy register comprises a plurality of memory locations; storing, in each of the plurality of memory locations, a value indicating a change was detected for the counter value corresponding to the plurality of hardware counters, wherein each of the plurality of hardware counters map to one of the plurality of memory locations; performing read operation on a subset of the hardware counters, wherein members of the subset of the hardware counters are determined based upon the value indicating that the change was detected for the counter value corresponding to the plurality of hardware counters; and resetting the value stored in all the memory locations to a default value.

Abstract: Embodiments include a system for performance monitoring, the system includes a processor configured to perform a method. The method includes detecting, by a redundancy register, a change to a counter value corresponding to one of a plurality of hardware counters, wherein the redundancy register comprises a plurality of memory locations; storing, in each of the plurality of memory locations, a value indicating a change was detected for the counter value corresponding to the plurality of hardware counters, wherein each of the plurality of hardware counters map to one of the plurality of memory locations; performing read operation on a subset of the hardware counters, wherein members of the subset of the hardware counters are determined based upon the value indicating that the change was detected for the counter value corresponding to the plurality of hardware counters; and resetting the value stored in all the memory locations to a default value.

Abstract: A method for monitoring performance of events occurring in a multiprocessor system is provided where the performance monitoring units (PMUs) are globally synchronized. The global synchronization is carried out with a dedicated bit field set to any of pause, stop, restart, or reset command. The command is sent across the scan communications interface (SCOM) of all chips by using existing fabric connecting all nest units to control the PMUs in the system. A pre-scale counter before a main counter may be used to buffer event counts until a reset or a restart command is sent to the SCOM in the system.