Patents by Inventor Srinivas Rao Kamepalli

Srinivas Rao Kamepalli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8209553
    Abstract: An information handling system (“IHS”) including a processor, a memory controller coupled to the processor, and a memory device interface coupled to the memory controller is provided. The IHS also includes a voltage control circuit, coupled to the interface, for determining whether the interface is coupled to a memory expansion board or a memory device. In response to determining that the interface is coupled to a memory device, the circuit activates a first voltage regulator for supplying a first level of voltage. In response to determining that the interface is coupled to a memory expansion board, the circuit activates a second voltage regulator for supplying a second level of voltage.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: June 26, 2012
    Assignee: Dell Products, L.P.
    Inventors: Srinivas Rao Kamepalli, Ajay Kwatra
  • Patent number: 7546472
    Abstract: An information handling system (“IHS”) including a processor, a memory controller coupled to the processor, and a memory device interface coupled to the memory controller is provided. The IHS also includes a voltage control circuit, coupled to the interface, for determining whether the interface is coupled to a memory expansion board or a memory device. In response to determining that the interface is coupled to a memory device, the circuit activates a first voltage regulator for supplying a first level of voltage. In response to determining that the interface is coupled to a memory expansion board, the circuit activates a second voltage regulator for supplying a second level of voltage.
    Type: Grant
    Filed: April 15, 2005
    Date of Patent: June 9, 2009
    Assignee: Dell Products L.P.
    Inventors: Srinivas Rao Kamepalli, Ajay Kwatra
  • Publication number: 20090138741
    Abstract: An information handling system (“IHS”) including a processor, a memory controller coupled to the processor, and a memory device interface coupled to the memory controller is provided. The IHS also includes a voltage control circuit, coupled to the interface, for determining whether the interface is coupled to a memory expansion board or a memory device. In response to determining that the interface is coupled to a memory device, the circuit activates a first voltage regulator for supplying a first level of voltage. In response to determining that the interface is coupled to a memory expansion board, the circuit activates a second voltage regulator for supplying a second level of voltage.
    Type: Application
    Filed: January 30, 2009
    Publication date: May 28, 2009
    Applicant: DELL PRODUCTS L.P.
    Inventors: Srinivas Rao Kamepalli, Ajay Kwatra
  • Patent number: 6425025
    Abstract: A bus includes at least a pair of terminators interposed between a pair of connectors. A first one of the terminators is located within a predetermined distance from a first one of the connectors. A second one of the terminators is located within the predetermined distance from a second one of the connectors. The second terminator is selectively disabled in response to the second terminator being interposed between the first terminator and a third terminator of the bus.
    Type: Grant
    Filed: June 3, 1999
    Date of Patent: July 23, 2002
    Assignee: Dell USA, L.P.
    Inventor: Srinivas Rao Kamepalli