Patents by Inventor Srinivas SWAMINATHAN
Srinivas SWAMINATHAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11925474Abstract: The present disclosure is directed to systems and methods for developing an individual-specific patient baseline for a target patient. An exemplary method involves: determining one or more acuity scores for the target patient; identifying patient health data corresponding to one or more low acuity time periods; storing retrospective clinical data from a group of patients in a second database; comparing the patient health data corresponding to the one or more low acuity time periods with retrospective clinical data from a group of patients by identifying one or more patient subgroups; determining the individual-specific patient baseline using an adaptive baseline selection algorithm, wherein the adaptive baseline selection algorithm is used to determine whether to determine the individual-specific patient baseline using patient health data or using retrospective clinical data from one or more patient subgroups; and displaying, using a user interface, the individual-specific patient baseline.Type: GrantFiled: July 2, 2020Date of Patent: March 12, 2024Assignee: KONINKLIJKE PHILIPS N.V.Inventors: Claire Yunzhu Zhao, Bryan Conroy, Mohammad Shahed Sorower, David Paul Noren, Kailash Swaminathan, Chaitanya Kulkarni, Ting Feng, Kristen Tgavalekos, Emma Holdrich Schwager, Erina Ghosh, Vinod Kumar, Vikram Shivanna, Srinivas Hariharan, Daniel Craig McFarlane
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Publication number: 20230327806Abstract: A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.Type: ApplicationFiled: June 16, 2023Publication date: October 12, 2023Inventors: Jamal RIANI, Benjamin Smith, Volodymyr Shvydun, Srinivas Swaminathan, Arash Farhoodfar
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Patent number: 11683124Abstract: A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.Type: GrantFiled: February 22, 2022Date of Patent: June 20, 2023Assignee: Marvell Asia Pte Ltd.Inventors: Jamal Riani, Benjamin Smith, Volodymyr Shvydun, Srinivas Swaminathan, Arash Farhoodfar
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Publication number: 20230185757Abstract: A multi-lane integrated circuit transceiver device includes first and second integrated circuit dies having respective first and second pluralities of transmit block/receive block pairs. Each respective transmit block and each respective receive block in the first plurality of block pairs on the first die and the second plurality of block pairs on the second die includes respective digital clock generation circuitry. The device further includes digital clock distribution circuitry to distribute a digital clock signal output by one respective receive block, in one of the first and second pluralities of block pairs, to the transmit blocks in both of the pluralities of block pairs, for use as a baseline clock by the respective digital clock generation circuitry in each of the transmit blocks in both of the pluralities of block pairs. Where each plurality includes N block pairs, the two dies together form a single 2N-lane device.Type: ApplicationFiled: December 8, 2022Publication date: June 15, 2023Inventors: Michael Lewis Takefman, Arash Farhoodfar, Srinivas Swaminathan, Belal Helal
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Publication number: 20220173833Abstract: A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.Type: ApplicationFiled: February 22, 2022Publication date: June 2, 2022Inventors: Jamal RIANI, Benjamin SMITH, Volodymyr SHVYDUN, Srinivas SWAMINATHAN, Arash FARHOODFAR
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Patent number: 11265109Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that processes an interleaved data stream and generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.Type: GrantFiled: March 19, 2020Date of Patent: March 1, 2022Assignee: Marvell Asia Pte Ltd.Inventors: Jamal Riani, Benjamin Smith, Volodymyr Shvydun, Srinivas Swaminathan, Arash Farhoodfar
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Publication number: 20200220659Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that processes an interleaved data stream and generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.Type: ApplicationFiled: March 19, 2020Publication date: July 9, 2020Inventors: Jamal RIANI, Benjamin SMITH, Volodymyr SHVYDUN, Srinivas SWAMINATHAN, Arash Farhoodfar