Abstract: A system includes a data path and a phase-locked loop (PLL) coupled to the data path. The system also includes a voltage-controlled oscillator (VCO) coupled to the PLL. The VCO includes an LC circuit with first and second differential output terminals. The VCO also includes a first resistor coupled between the first differential output terminal and drain terminals of a first pair of complementary metal-oxide semiconductor (CMOS) transistors. The VCO also includes a second resistor coupled between the second differential output terminal and drain terminals of a second pair of CMOS transistors.

Abstract: A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.

Abstract: A system includes a data path and a phase-locked loop (PLL) coupled to the data path. The system also includes a voltage-controlled oscillator (VCO) coupled to the PLL. The VCO includes an LC circuit with first and second differential output terminals. The VCO also includes a first resistor coupled between the first differential output terminal and drain terminals of a first pair of complementary metal-oxide semiconductor (CMOS) transistors. The VCO also includes a second resistor coupled between the second differential output terminal and drain terminals of a second pair of CMOS transistors.

Abstract: A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.

Abstract: A system includes a data path and a phase-locked loop (PLL) coupled to the data path. The system also includes a voltage-controlled oscillator (VCO) coupled to the PLL. The VCO includes an LC circuit with first and second differential output terminals. The VCO also includes a first resistor coupled between the first differential output terminal and drain terminals of a first pair of complementary metal-oxide semiconductor (CMOS) transistors. The VCO also includes a second resistor coupled between the second differential output terminal and drain terminals of a second pair of CMOS transistors.

Abstract: In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.

Abstract: Frequency synthesis is based on phase synchronizing PLL output across REFERENCE and VCO clock domains (including outputs for multiple PLLs), based on an input (REF-Domain) SYNC signal (phase timing reference). A frequency synthesizer includes a VCO to generate VCO_clk and a PLL output circuit, such as a channel divider, to generate PLL_OUT based on VCO_clk (in the VCO-Domain). The VCO loop includes a PD to phase compare an input PD_clock based on REF_CLK, and a VCO feedback signal based on divided VCO_clk (NDIV_out). SYNC alignment circuitry generates a SYNC alignment signal based on SYNC, PD_clk, and NDIV_out (REF-Domain), which is used to synchronize the PLL output circuit and PLL_OUT to SYNC. If a reference divider generates PD_clk, the SYNC alignment circuitry generates a reset to SYNC-align the reference divider. If the VCO loop uses fractional divide, the SYNC alignment circuitry resets the fractional modulator to a known sequence.

Abstract: In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.

Abstract: In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.

Abstract: The disclosure provides a frequency synthesizer. It includes a PFD that generates an up signal and a down signal in response to a reference signal and a feedback signal. A charge pump generates a control voltage in response to the up signal and the down signal. A low pass filter generates a filtered voltage in response to the control voltage. An oscillator circuit generates an output signal in response to the filtered voltage. A feedback divider is coupled between the oscillator circuit and the PFD, and divides the output signal by a first integer divider to generate the feedback signal. A sigma delta modulator (SDM) generates a second integer divider in response to the feedback signal, the reference signal, the output signal and the first integer divider. A digital filter is coupled between the SDM and the feedback divider, and filters quantization noise associated with the SDM.

Abstract: In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.

Abstract: The disclosure provides a frequency synthesizer. It includes a PFD that generates an up signal and a down signal in response to a reference signal and a feedback signal. A charge pump generates a control voltage in response to the up signal and the down signal. A low pass filter generates a filtered voltage in response to the control voltage. An oscillator circuit generates an output signal in response to the filtered voltage. A feedback divider is coupled between the oscillator circuit and the PFD, and divides the output signal by a first integer divider to generate the feedback signal. A sigma delta modulator (SDM) generates a second integer divider in response to the feedback signal, the reference signal, the output signal and the first integer divider. A digital filter is coupled between the SDM and the feedback divider, and filters quantization noise associated with the SDM.