Abstract: Aspects of the disclosure are directed to a high performance connection scheduler for reliable transport protocols in data center networking. The connection scheduler can handle enqueue events, dequeue events, and update events. The connection scheduler can include a connection queue, scheduling queue, and quality of service arbiter to support scheduling a large number of connections at a high rate.

Abstract: Aspects of the disclosure are directed to a memory allocator for assigning contiguous memory space for data packets in on-chip memory of a network interface card. The memory allocator includes a plurality of sub-allocators that correspond to a structure of entries, where each entry represents a quanta of memory allocation. The sub-allocators are organized in decreasing size in the memory allocator based on the amount of memory quanta they can allocate.

Abstract: A hash table system, including a plurality of hash tables, associated with respective hash functions, for storing key-value pairs; an overflow memory for storing key-value pairs moved from the hash tables due to collision; and an arbiter for arbitrating among commands including update commands, match commands, and rehash commands, wherein for each system clock cycle, the arbiter selects as a selected command one of an update command, a match command, or a rehash command, and wherein the hash table system completes execution of each selected command within a bounded number of system clock cycles.

Abstract: Compressing connection state information for a network connection including receiving an input bitmap having a sequence of bits describing transmit states and receive states; partitioning the input bitmap into a plurality of equal size blocks; partitioning each of the blocks into a plurality of equal sized sectors; generating a block valid sequence indicating the blocks having at least one bit set; generating, for each block having at least one bit set, a sector information sequence, the sector information sequence indicating, for the corresponding block, the sectors that have at least one bit set and an encoding type for each sector; and generating one or more symbols by encoding each sector that has at least one bit set.

Abstract: The technology is directed to the use of a bitmap generated at a receiver to track the status of received packets sent by a transmitter. The technology may include a network device including an input port, output port, and circuitry. The circuitry may generate a transmitter bitmap that tracks each data packet sent to another network device. The circuitry of the network device may receive, from the other network device, a receiver bitmap that identifies each data packet that is received and not received from the network device. The circuitry may then determine which data packets to retransmit by comparing the transmitter bitmap to the receiver bitmap.

Abstract: Aspects of the disclosure are directed to high performance connection cache eviction for reliable transport protocols in data center networking. Connection priorities for connection entries are determined to store the connection entries in a cache based on their connection priority. During cache eviction, the connection entries with a lowest connection priority are evicted from the cache. Cache eviction can be achieved with low latency at a high rate.

Abstract: A communication protocol system is provided for reliable transport of packets. In this regard, an initiator entity may determine that outgoing data is to be transmitted to a target entity. The initiator entity may transmit, to the target entity, a solicited push request requesting the outgoing data to be placed at the target entity. In response to the solicited push request, the initiator entity may receive a push grant from the target entity. In response to the push grant, the initiator entity may transmit to the target entity the outgoing data to be placed at the target entity.

Abstract: A hash table system, including a plurality of hash tables, associated with respective hash functions, for storing key-value pairs; an overflow memory for storing key-value pairs moved from the hash tables due to collision; and an arbiter for arbitrating among commands including update commands, match commands, and rehash commands, wherein for each system clock cycle, the arbiter selects as a selected command one of an update command, a match command, or a rehash command, and wherein the hash table system completes execution of each selected command within a bounded number of system clock cycles.

Abstract: A packet cache system includes a cache memory allocator for receiving a memory address corresponding to a non-cache memory and allocated to a packet, and associating the memory address with a cache memory address; a hash table for storing the memory address and the cache memory address, with the memory address as a key and the cache memory address as a value; a cache memory for storing the packet at a location indicated by the cache memory address; and an eviction engine for determining one or more cached packets to remove from the cache memory and place in the non-cache memory when occupancy of the cache memory is high.

Abstract: A communication protocol system is provided for reliable transport of packets. Transport of packets includes transmitting, by a sender entity over a connection to a receiver entity, a plurality of packets in a first order, maintaining, by the sender entity, one or more sliding windows including a plurality of bits, wherein each bit of the sliding window represents a respective packet of the plurality of packets, receiving, by the sender entity, one or more acknowledgments indicating that one or more of the plurality of packets have been received by the receiver entity, each of the acknowledgments referencing a respective packet of the plurality of packets and modifying, by the sender entity, values of one or more of the plurality of bits in the sliding window corresponding to the one or more acknowledgments received.

Abstract: An application specific integrated circuit (ASIC) is provided for reliable transport of packets. The network interface card may include a reliable transport accelerator (RTA). The RTA may include a cache lookup database. The RTA may be configured to determine, from a received data packet, a connection identifier and query the cache lookup database for a cache entry corresponding to a connection context having the connection identifier. In response to the query, the RTA may receive a cache hit or a cache miss.

Abstract: A communication protocol system is provided for reliable transport of packets. A content addressable memory hardware architecture including an acknowledgment coalescing module in communication with a content addressable memory (CAM). The acknowledgment coalescing module coalesces multiple acknowledgement packets as a single acknowledgement packet to reduce the overall numbers of the packet transmission in the communication protocol system. In addition, the acknowledgment coalescing module may also provide a piggyback mechanism to carry acknowledge information in a regular data packet. Thus, the need to generate a new acknowledgement packet may be eliminated. Accordingly, the network congestion and latency may be reduced, and the communication and transmission efficiency are enhanced.

Abstract: A communication protocol system is provided for reliable transport of packets. A content addressable memory hardware architecture including a reorder engine and a retransmission engine may be utilized for the reliable transport of the packets. The content addressable memory module includes a primary CAM that may be logically partitioned into a plurality of physical sub-CAMs. One or more processors are in communication with the content addressable memory module. The one or more processors receive a set of data packets. A lookup operation is performed by the one or more processors to access data entries stored in each of the sub-content addressable memories. An update operation is performed by the one or more processors at a selected sub-content addressable memory from the plurality of the sub-content addressable memories.

Abstract: A communication protocol system is provided for reliable transport of packets. In this regard, an initiator entity may determine that outgoing data is to be transmitted to a target entity. The initiator entity may transmit, to the target entity, a solicited push request requesting the outgoing data to be placed at the target entity. In response to the solicited push request, the initiator entity may receive a push grant from the target entity. In response to the push grant, the initiator entity may transmit to the target entity the outgoing data to be placed at the target entity.

Abstract: A communication protocol system is provided for reliable transport of packets. In this regard, an initiator entity may determine that outgoing data is to be transmitted to a target entity. The initiator entity may transmit, to the target entity, a solicited push request requesting the outgoing data to be placed at the target entity. In response to the solicited push request, the initiator entity may receive a push grant from the target entity. In response to the push grant, the initiator entity may transmit to the target entity the outgoing data to be placed at the target entity.

Abstract: A communication protocol system is provided for reliable transport of packets. A content addressable memory hardware architecture including a reorder engine and a retransmission engine may be utilized for the reliable transport of the packets. In this regard, a reorder engine includes a content addressable memory (CAM) and one or more processors in communication with the CAM. The one or more processors are configured to receive a first set of data packets when executed by the one or more processors. The one or more processors are configured to access the content addressable memory to process the first set of data packets. The one or more processors are configured to save data information of the first set of the data packets in the content addressable memory.

Abstract: A communication protocol system is provided for reliable transport of packets. A content addressable memory hardware architecture including a reorder engine and a retransmission engine may be utilized for the reliable transport of the packets. In this regard, a reorder engine includes a content addressable memory (CAM) and one or more processors in communication with the CAM. The one or more processors are configured to receive a first set of data packets when executed by the one or more processors. The one or more processors are configured to access the content addressable memory to process the first set of data packets. The one or more processors are configured to save data information of the first set of the data packets in the content addressable memory.

Abstract: A communication protocol system is provided for reliable transport of packets. In this regard, an initiator entity may determine that outgoing data is to be transmitted to a target entity. The initiator entity may transmit, to the target entity, a solicited push request requesting the outgoing data to be placed at the target entity. In response to the solicited push request, the initiator entity may receive a push grant from the target entity. In response to the push grant, the initiator entity may transmit to the target entity the outgoing data to be placed at the target entity.

Abstract: An apparatus includes a scheduler module operatively coupled to each memory block from a set of memory blocks via a shared address bus. The scheduler module is configured to receive a group of memory commands from a set of memory controllers. Each memory controller from the set of memory controllers is uniquely associated with a different memory block from the set of memory blocks. The scheduler module is configured to classify each memory command from the group of memory commands into a category based at least in part on memory commands previously sent to the set of memory blocks via the shared address bus. The scheduler module is configured to select an order in which to send each memory command from the group of memory commands to the set of memory blocks via the shared address bus based at least in part on the category of each memory command.

Abstract: An apparatus includes a scheduler module operatively coupled to each memory block from a set of memory blocks via a shared address bus. The scheduler module is configured to receive a group of memory commands from a set of memory controllers. Each memory controller from the set of memory controllers is uniquely associated with a different memory block from the set of memory blocks. The scheduler module is configured to classify each memory command from the group of memory commands into a category based at least in part on memory commands previously sent to the set of memory blocks via the shared address bus. The scheduler module is configured to select an order in which to send each memory command from the group of memory commands to the set of memory blocks via the shared address bus based at least in part on the category of each memory command.