Abstract: Data Center (DC) server power management monitors resource utilization and energy consumption characteristics of an individual host server, and a Virtual Machine (VM) and the applications running inside any VM of DC servers. An analysis and learning module identifies trends and opportunities to optimize DC resources by releasing the underutilized host servers. It derives power metrics to measure the energy footprint of the VMs and the associated applications. It suggests optimal destination servers to migrate each of the VMs with corresponding applications from the underutilized host servers. The power consumption of these VMs with their applications on the power-efficient destination servers is less after the migration. Powering off the underutilized freed-up servers saves energy impacting the overall power consumption of the data center.

Abstract: Data Center (DC) server power management monitors resource utilization and energy consumption characteristics of an individual host server, and a Virtual Machine (VM) and the applications running inside any VM of DC servers. An analysis and learning module identifies trends and opportunities to optimize DC resources by releasing the underutilized host servers. It derives power metrics to measure the energy footprint of the VMs and the associated applications. It suggests optimal destination servers to migrate each of the VMs with corresponding applications from the underutilized host servers. The power consumption of these VMs with their applications on the power-efficient destination servers is less after the migration. Powering off the underutilized freed-up servers saves energy impacting the overall power consumption of the data center.

Abstract: A system including an intelligent power management device including a plurality of sub-devices, a communication component communicatively connect the device to a communication network, wherein an intelligent power management (IPM) agent is continually run on the device and is configured to save power consumption on the device based on a plurality of power management policies including power management actions for controlling power consumption of a sub-device, wherein the power management policy is received from a remote server, and wherein the IPM agent is configured to adaptively change, using historic usage data of a plurality of users of the intelligent power management device, the power management actions to optimize a power saving on the plurality of sub-devices for each of the plurality of users.

Abstract: A system including an intelligent power management device including a plurality of sub-devices, a communication component communicatively connect the device to a communication network, wherein an intelligent power management (IPM) agent is continually run on the device and is configured to save power consumption on the device based on a plurality of power management policies including power management actions for controlling power consumption of a sub-device, wherein the power management policy is received from a remote server, and wherein the IPM agent is configured to adaptively change, using historic usage data of a plurality of users of the intelligent power management device, the power management actions to optimize a power saving on the plurality of sub-devices for each of the plurality of users.

Abstract: A peak power management system for networked smart IT devices. These smart devices have computing capability with at least one CPU and memory and can be networked. An uninterruptible power supply provides power to the smart devices. A central intelligent power management server controls the power consumed by all the smart devices networked with the server. The system uses priority based peak power management policies for smart IT devices assisted by fine grain control of external power drawn by each device. By applying different power management policies at different scheduled intervals and controlling the power consumption on the smart devices, the aggregated peak power demand is controlled. The policies can be adapted in-time to suit the actual, real-time power requirement of devices, their priorities, and applicable peak power limit at that time. Also, dynamic policy based peak power management can be extended to an intelligent hierarchical power distribution network.

Abstract: A peak power management system for networked smart IT devices. These smart devices have computing capability with at least one CPU and memory and can be networked. An uninterruptible power supply provides power to the smart devices. A central intelligent power management server controls the power consumed by all the smart devices networked with the server. The system uses priority based peak power management policies for smart IT devices assisted by fine grain control of external power drawn by each device. By applying different power management policies at different scheduled intervals and controlling the power consumption on the smart devices, the aggregated peak power demand is controlled. The policies can be adapted in-time to suit the actual, real-time power requirement of devices, their priorities, and applicable peak power limit at that time. Also, dynamic policy based peak power management can be extended to an intelligent hierarchical power distribution network.

Abstract: A system and method of ensuring hardware security of a device, such as an integrated circuit having secure data stored thereon. The integrated circuit or other hardware device can implement one or more configurable fuses that limit access to one or more secure locations within the device. The secure locations may contain secure data. The state of the configurable fuses can be ensured, thereby limiting access to secure locations, by forcing the occurrence of a logical state prior to allowing access to hardware locations configured by the fuses. A configurable non-secure access code can be used to force the occurrence of the logical state. Receipt of the non-secure access code by the hardware device forces the occurrence of the hardware state, thereby ensuring access only to those secure locations configured by the fuses.

Abstract: A power management system includes a power management agent and a computing device comprising a CPU, memory, persistent storage, operating system, and communication mechanism. A power management server communicates with the communication mechanism using a secure communication protocol, communicates with the power management agent when the agent is in the connected mode, and provides a non-intrusiveness monitoring function. The power management agent operates in both a connected and disconnected mode, and maintains a list of applications, tasks, and activities and their dependency on power manageable components in the device. An application control framework defines a non-intrusiveness of a device for every application on the device and a usage of the device to allow fine grain control of the device. A management station sends a set of monitoring commands to at least one agent to monitor the intrusiveness of a power management function on the device without enforcing any power management.

Abstract: A power management system includes a power management agent and a computing device comprising a CPU, memory, persistent storage, operating system, and communication mechanism. A power management server communicates with the communication mechanism using a secure communication protocol, communicates with the power management agent when the agent is in the connected mode, and provides a non-intrusiveness monitoring function. The power management agent operates in both a connected and disconnected mode, and maintains a list of applications, tasks, and activities and their dependency on power manageable components in the device. An application control framework defines a non-intrusiveness of a device for every application on the device and a usage of the device to allow fine grain control of the device. A management station sends a set of monitoring commands to at least one agent to monitor the intrusiveness of a power management function on the device without enforcing any power management.

Abstract: An integrated circuit that supports testing of multiple pads via a subset of these pads includes at least two sections. Each section has multiple pads and multiple test access circuits coupled to these pads. For each section, one pad is designated as a primary pad and the remaining pads are designated as secondary pads. For each section, the test access circuits couple the secondary pads to the primary pad such that all of the pads in the section can be tested by probing just the primary pad. Each test access circuit may be implemented with a simple switch. A controller generates a set of control signals for the test access circuits in all sections. These control signals enable and disable the test access circuits such that all of the sections can be tested in parallel, and the pads in each section can be tested in a sequential order.

Abstract: An integrated circuit that supports testing of multiple pads via a subset of these pads includes at least two sections. Each section has multiple pads and multiple test access circuits coupled to these pads. For each section, one pad is designated as a primary pad and the remaining pads are designated as secondary pads. For each section, the test access circuits couple the secondary pads to the primary pad such that all of the pads in the section can be tested by probing just the primary pad. Each test access circuit may be implemented with a simple switch. A controller generates a set of control signals for the test access circuits in all sections. These control signals enable and disable the test access circuits such that all of the sections can be tested in parallel, and the pads in each section can be tested in a sequential order.

Abstract: An integrated circuit that supports testing of multiple pads via a subset of these pads includes at least two sections. Each section has multiple pads and multiple test access circuits coupled to these pads. For each section, one pad is designated as a primary pad and the remaining pads are designated as secondary pads. For each section, the test access circuits couple the secondary pads to the primary pad such that all of the pads in the section can be tested by probing just the primary pad. Each test access circuit may be implemented with a simple switch. A controller generates a set of control signals for the test access circuits in all sections. These control signals enable and disable the test access circuits such that all of the sections can be tested in parallel, and the pads in each section can be tested in a sequential order.

Abstract: A pilot searcher for CDMA and GPS signals. In one aspect, the searcher is operated in conjunction with a sample buffer in a “real-time” or “off-line” mode. The writing/reading of samples to/from the buffer may be performed in a TDM manner via a common port, and samples may be decimated and packed prior to storing in the buffer. In another aspect, the overall search for pilots is partitioned into a number of tasks, with each task corresponding to a search over a given sample segment and based on a particular set of parameter values. The tasks may be stored in a queue and performed one at a time based on their order in the queue. Prior to performing a new task, the parameter values for that task is downloaded to a set of configuration registers. The parameters may be ordered and linked such that only new values are downloaded.

Abstract: A Test Access Port (TAP) switch provides a centralized serial test interface between an electronic system and a resource external to the electronic system. The electronic system includes the TAP switch and a plurality of electronic circuit components, each electronic circuit component having a TAP coupled to the TAP switch. In one or more embodiments, the TAP switch comprises a first circuit configured to provide a clock signal to a selected one of the TAPs responsive to a selection code included in a serialized instruction, e.g., a code appended or prepended to the instruction. The TAP switch further comprises a second circuit comprising an instruction register (IR) configured to pass serialized instructions received by the TAP switch to the selected TAP and a third circuit configured to forward serialized data received from the selected TAP to an output of the TAP switch responsive to the selection code.

Abstract: An integrated circuit that supports testing of multiple pads via a subset of these pads includes at least two sections. Each section has multiple pads and multiple test access circuits coupled to these pads. For each section, one pad is designated as a primary pad and the remaining pads are designated as secondary pads. For each section, the test access circuits couple the secondary pads to the primary pad such that all of the pads in the section can be tested by probing just the primary pad. Each test access circuit may be implemented with a simple switch. A controller generates a set of control signals for the test access circuits in all sections. These control signals enable and disable the test access circuits such that all of the sections can be tested in parallel, and the pads in each section can be tested in a sequential order.

Abstract: A common programming interface in a communication subsystem controller allows protocols to be developed or modified to communicate with the communication subsystem controller. Once a protocol layer is able to communicate with the communication subsystem controller, the protocol layer is stacked with other protocol layers compatible with the communication subsystem controller. A table in the communication subsystem controller specifies an order of protocol layers in the protocol stack. These protocol layers in the protocol stack communicate with their adjacent protocol layers through the communication subsystem controller.

Abstract: A computer software engineering process monitoring application for monitoring a project including a software engineering process is disclosed. The computer software engineering process monitoring application comprising, a plurality of software engineering process monitoring program modules. Each module is configured to monitor at least one attribute of the software engineering process on the basis of one or more software engineering process attribute metrics. The application further comprises an updateable database structure configured to store thereon monitoring data including software engineering process attribute metric data useable by one or more of the program modules and a user interface module for generating a user accessible interface representing an output of at least one of the monitoring program modules.

Abstract: A system and method of ensuring hardware security of a device, such as an integrated circuit having secure data stored thereon. The integrated circuit or other hardware device can implement one or more configurable fuses that limit access to one or more secure locations within the device. The secure locations may contain secure data. The state of the configurable fuses can be ensured, thereby limiting access to secure locations, by forcing the occurrence of a logical state prior to allowing access to hardware locations configured by the fuses. A configurable non-secure access code can be used to force the occurrence of the logical state. Receipt of the non-secure access code by the hardware device forces the occurrence of the hardware state, thereby ensuring access only to those secure locations configured by the fuses.

Abstract: A common programming interface in a communication subsystem controller allows protocols to be developed or modified to communicate with the communication subsystem controller. Once a protocol layer is able to communicate with the communication subsystem controller, the protocol layer is stacked with other protocol layers compatible with the communication subsystem controller. A table in the communication subsystem controller specifies an order of protocol layers in the protocol stack. These protocol layers in the protocol stack communicate with their adjacent protocol layers through the communications subsystem controller.

Abstract: A common programming interface in a communication subsystem controller allows protocols to be developed or modified to communicate with the communication subsystem controller. Once a protocol layer is able to communicate with the communication subsystem controller, the protocol layer is stacked with other protocol layers compatible with the communication subsystem controller. A table in the communication subsystem controller specifies an order of protocol layers in the protocol stack. These protocol layers in the protocol stack communicate with their adjacent protocol layers through the communication subsystem controller. The communication subsystem controller does not have knowledge of any protocol specific information as the protocol specific information resides only with each protocol layer. Error recovery is built into the communication subsystem controller.