Abstract: An example method of calibrating a source-synchronous system includes: performing initial calibration of a source-synchronous receiver, which is configured to receive data signals and a strobe, to determine an initial strobe delay and initial data delays; setting a strobe delay circuit that delays the strobe to have the initial strobe delay and data delay circuits that delay the data signals to have the initial data delays; measuring first data eye margins of the data signals at a first time; calculating metrics for the data signals based on the first data eye margins; and measuring second data eye margins of the data signals at a second time; and updating the data delay circuits and the strobe delay circuit based on the second data eye margins and the metrics.

Abstract: An example method of calibrating a source-synchronous system includes: performing initial calibration of a source-synchronous receiver, which is configured to receive data signals and a strobe, to determine an initial strobe delay and initial data delays; setting a strobe delay circuit that delays the strobe to have the initial strobe delay and data delay circuits that delay the data signals to have the initial data delays; measuring first data eye margins of the data signals at a first time; calculating metrics for the data signals based on the first data eye margins; and measuring second data eye margins of the data signals at a second time; and updating the data delay circuits and the strobe delay circuit based on the second data eye margins and the metrics.

Abstract: A USB transceiver has transmitter circuitry, receiver circuitry, short-circuit detection circuitry, and short-circuit protection circuitry. The transmitter circuitry transmits a differential pair of outgoing data signals to a cable connected to the transceiver, and the receiver circuitry receives the differential pair of outgoing data signals via bi-directional input-output pins. The short-circuit detection circuitry analyzes each of the outgoing differential data signals to detect a short circuit in the pair of outgoing data signals, and the short-circuit protection circuitry protects the transmitter circuitry upon detection of a short circuit.

Abstract: Hardware-based methods and apparatus are provided for training high speed data links used in data transfer applications. A data valid window is calibrated on one or more high speed links by determining an offset delay value for at least one datapath using a finite state machine, wherein the offset delay value is based on a maximum offset delay value and a minimum offset delay value for the at least one datapath; and delaying a read data strobe signal based upon a base delay and the offset delay value for the at least one datapath. The offset delay value can be, for example, an average of the maximum offset delay and the minimum offset delay. The received pattern can be a predefined pattern or a programmable pattern. In addition, the received pattern can cover single-bit transitions and/or multi-bit transitions.

Abstract: Hardware-based methods and apparatus are provided for training high speed data links used in data transfer applications. A data valid window is calibrated on one or more high speed links by determining an offset delay value for at least one datapath using a finite state machine, wherein the offset delay value is based on a maximum offset delay value and a minimum offset delay value for the at least one datapath; and delaying a read data strobe signal based upon a base delay and the offset delay value for the at least one datapath. The offset delay value can be, for example, an average of the maximum offset delay and the minimum offset delay. The received pattern can be a predefined pattern or a programmable pattern. In addition, the received pattern can cover single-bit transitions and/or multi-bit transitions.

Abstract: A device and method for processing an incoming data stream in a half-rate clock elasticity first in first out (FIFO) are disclosed. In one embodiment, two data blocks are written substantially simultaneously to two locations in the elasticity FIFO specified by respective two write pointers in a write clock cycle of a write clock. Further, two data blocks are read substantially simultaneously from two consecutive or non-consecutive locations in the elasticity FIFO specified by two read pointers in a read clock cycle of a read clock. The two read pointers can independently adjust locations to read in the plurality of locations based on a type of the data blocks in the elasticity FIFO and a predetermined elasticity FIFO threshold level in the read clock cycle to maintain the elasticity FIFO level at predetermined elasticity FIFO threshold level to achieve a constant output rate.