Patents by Inventor Srinivasa Banna

Srinivasa Banna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230086869
    Abstract: This specification discloses LEDs and LED arrays configured such that an electric field may be applied during operation of the device to drive charge carriers (electrons or holes) away from perimeter semiconductor surfaces of the LEDs, thereby reducing non-radiative recombination near those perimeter surfaces. These LEDs and LED arrays comprise (e.g., metal) field plates, arranged around the perimeter surfaces of the LEDs, by which the electric field may be applied. In some variations, the bias voltage applied to the field plates to produce the electric fields may be separately controlled for some, or each, LED in an array. In other variations the bias applied to the field plates is the same for each LED in an array.
    Type: Application
    Filed: September 20, 2022
    Publication date: March 23, 2023
    Applicant: Lumileds LLC
    Inventors: Srinivasa Banna, Antonio Lopez-Julia, Joseph Flemish
  • Patent number: 10784402
    Abstract: Methods of forming an integrated InGaN/GaN or AlInGaP/InGaP LED on Si CMOS for RGB colors and the resulting devices are provided. Embodiments include forming trenches having a v-shaped bottom through an oxide layer and a portion of a substrate; forming AlN or GaAs in the v-shaped bottom; forming a n-GaN or n-InGaP pillar on the AlN or GaAs through and above the first oxide layer; forming an InGaN/GaN MQW or AlInGaP/InGaP MQW over the n-GaN or n-InGaP pillar; forming a p-GaN or p-InGaP layer over the n-GaN pillar and InGaN/GaN MQW or the n-InGaP pillar and AlInGaP/InGaP MQW down to the first oxide layer; forming a TCO layer over the first oxide layer and the p-GaN or p-InGaP layer; forming a second oxide layer over the TCO layer; and forming a metal pad on the TCO layer above each n-GaN or n-InGaP pillar.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: September 22, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Srinivasa Banna, Deepak Nayak
  • Patent number: 10396121
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs for light emitting diode displays and methods of manufacture. The method includes: forming replacement fin structures with a doped core region, on doped substrate material; forming quantum wells over the replacement fin structures; forming a first color emitting region by doping at least one of the quantum wells over at least a first replacement fin structure of the replacement fin structures, while protecting at least a second replacement fin structure of the replacement fin structures; and forming a second color emitting region by doping another one of the quantum wells over the at least second replacement fin structure of the replacement fin structures, while protecting the first replacement fin structure and other replacement fin structures which are not to be doped.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: August 27, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ajey P. Jacob, Srinivasa Banna, Deepak Nayak
  • Patent number: 10388691
    Abstract: A color stacked light emitting diode (LED) pixel is disclosed. The color stacked LED includes an LED pixel structure body, a base LED disposed on at least a portion of the LED pixel structure body, an intermediate LED disposed on the base LED, and a top LED disposed on the intermediate LED. The stacked LED may be an overlapping or a non-overlapping LED pixel. The LED pixel structure body may be a fin body or a nanowire body.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: August 20, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Srinivasa Banna, Deepak Nayak, Ajey P. Jacob
  • Publication number: 20190221708
    Abstract: Methods of forming an integrated InGaN/GaN or AlInGaP/InGaP LED on Si CMOS for RGB colors and the resulting devices are provided. Embodiments include forming trenches having a v-shaped bottom through an oxide layer and a portion of a substrate; forming AlN or GaAs in the v-shaped bottom; forming a n-GaN or n-InGaP pillar on the AlN or GaAs through and above the first oxide layer; forming an InGaN/GaN MQW or AlInGaP/InGaP MQW over the n-GaN or n-InGaP pillar; forming a p-GaN or p-InGaP layer over the n-GaN pillar and InGaN/GaN MQW or the n-InGaP pillar and AlInGaP/InGaP MQW down to the first oxide layer; forming a TCO layer over the first oxide layer and the p-GaN or p-InGaP layer; forming a second oxide layer over the TCO layer; and forming a metal pad on the TCO layer above each n-GaN or n-InGaP pillar.
    Type: Application
    Filed: March 27, 2019
    Publication date: July 18, 2019
    Inventors: Srinivasa BANNA, Deepak NAYAK
  • Patent number: 10290768
    Abstract: Methods of forming an integrated InGaN/GaN or AlInGaP/InGaP LED on Si CMOS for RGB colors and the resulting devices are provided. Embodiments include forming trenches having a v-shaped bottom through an oxide layer and a portion of a substrate; forming AlN or GaAs in the v-shaped bottom; forming a n-GaN or n-InGaP pillar on the AlN or GaAs through and above the first oxide layer; forming an InGaN/GaN MQW or AlInGaP/InGaP MQW over the n-GaN or n-InGaP pillar; forming a p-GaN or p-InGaP layer over the n-GaN pillar and InGaN/GaN MQW or the n-InGaP pillar and AlInGaP/InGaP MQW down to the first oxide layer; forming a TCO layer over the first oxide layer and the p-GaN or p-InGaP layer; forming a second oxide layer over the TCO layer; and forming a metal pad on the TCO layer above each n-GaN or n-InGaP pillar.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Srinivasa Banna, Deepak Nayak
  • Patent number: 10283560
    Abstract: Disclosed is a device which includes first and second major substrate surfaces. The first substrate surface includes an LED with first and second terminals while the second substrate surface includes CMOS circuit components. The CMOS components and LED are coupled by through silicon via (TSV) contacts which extend through the second substrate surface.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: May 7, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Deepak Nayak, Srinivasa Banna, Ajey P. Jacob
  • Patent number: 10263151
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to light emitting diodes and methods of manufacture. The method includes: forming fin structures with a doped core region, on a substrate material; forming a first color emitting region by cladding the doped core region of a first fin structure of the fin structures, while protecting the doped core regions of a second fin structure and a third fin structure of the fin structures; forming a second color emitting region by cladding the doped core region of the second fin structure, while protecting the doped core regions of the first fin structure and the third fin structure; and forming a third color emitting region by cladding the doped core region of the third fin structure, while protecting the doped core regions of the first fin structure and the second fin structure.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: April 16, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ajey P. Jacob, Srinivasa Banna, Deepak Nayak
  • Publication number: 20190081206
    Abstract: Methods of forming an integrated InGaN/GaN or AlInGaP/InGaP LED on Si CMOS for RGB colors and the resulting devices are provided. Embodiments include forming trenches having a v-shaped bottom through an oxide layer and a portion of a substrate; forming AlN or GaAs in the v-shaped bottom; forming a n-GaN or n-InGaP pillar on the AlN or GaAs through and above the first oxide layer; forming an InGaN/GaN MQW or AlInGaP/InGaP MQW over the n-GaN or n-InGaP pillar; forming a p-GaN or p-InGaP layer over the n-GaN pillar and InGaN/GaN MQW or the n-InGaP pillar and AlInGaP/InGaP MQW down to the first oxide layer; forming a TCO layer over the first oxide layer and the p-GaN or p-InGaP layer; forming a second oxide layer over the TCO layer; and forming a metal pad on the TCO layer above each n-GaN or n-InGaP pillar.
    Type: Application
    Filed: September 14, 2017
    Publication date: March 14, 2019
    Inventors: Srinivasa BANNA, Deepak NAYAK
  • Publication number: 20190058087
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to light emitting diodes and methods of manufacture. The method includes: forming fin structures with a doped core region, on a substrate material; forming a first color emitting region by cladding the doped core region of a first fin structure of the fin structures, while protecting the doped core regions of a second fin structure and a third fin structure of the fin structures; forming a second color emitting region by cladding the doped core region of the second fin structure, while protecting the doped core regions of the first fin structure and the third fin structure; and forming a third color emitting region by cladding the doped core region of the third fin structure, while protecting the doped core regions of the first fin structure and the second fin structure.
    Type: Application
    Filed: August 18, 2017
    Publication date: February 21, 2019
    Inventors: Ajey P. Jacob, Srinivasa Banna, Deepak Nayak
  • Publication number: 20190058002
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs for light emitting diode displays and methods of manufacture. The method includes: forming replacement fin structures with a doped core region, on doped substrate material; forming quantum wells over the replacement fin structures; forming a first color emitting region by doping at least one of the quantum wells over at least a first replacement fin structure of the replacement fin structures, while protecting at least a second replacement fin structure of the replacement fin structures; and forming a second color emitting region by doping another one of the quantum wells over the at least second replacement fin structure of the replacement fin structures, while protecting the first replacement fin structure and other replacement fin structures which are not to be doped.
    Type: Application
    Filed: August 18, 2017
    Publication date: February 21, 2019
    Inventors: Ajey P. Jacob, Srinivasa Banna, Deepak Nayak
  • Patent number: 10199429
    Abstract: Devices and methods of forming the devices are disclosed. The device includes a substrate and a color LED pixel disposed on the substrate. The color LED pixel includes a red LED, a green LED and a blue LED. Each of the color LED includes a specific color LED body disposed on the respective color region on the substrate, a specific color multiple quantum well (MQW) on the respective color LED body and a specific color top LED layer disposed over the respective color MQW. The MQWs of the red LED, green LED and blue LED includes at least an indium gallium nitride (InxGa1-xN) layer and a gallium nitride (GaN), where x is the atomic percentage of In in the InxGa1-xN layer, and the MQWs of the red LED, green LED and blue LED have different bandgaps by varying x of the InxGa1-xN layer in the red LED, the green LED and the blue LED.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Srinivasa Banna, Deepak Nayak, Ajey P. Jacob
  • Patent number: 10193011
    Abstract: Methods of forming an integrated RGB LED and Si CMOS driver wafer and the resulting devices are provided. Embodiments include providing a plurality of first color die over a CMOS wafer, each first color die being laterally separated with a first oxide and electrically connected to the CMOS wafer; providing a second color die above each first color die, each second color die being separated from each other with a second oxide, bonded to a first color die, and electrically connected to the CMOS wafer through the bonded first color die; removing a portion of each second color die to expose a portion of each bonded first color die; forming a conformal TCO layer over each first and second color die and on a side surface of each second color die and oxide; forming a PECVD oxide layer over the CMOS wafer; and planarizing the PECVD oxide layer.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Srinivasa Banna, Deepak Nayak, Luke England, Rahul Agarwal
  • Publication number: 20190019915
    Abstract: Methods of forming an integrated RGB LED and Si CMOS driver wafer and the resulting devices are provided. Embodiments include providing a plurality of first color die over a CMOS wafer, each first color die being laterally separated with a first oxide and electrically connected to the CMOS wafer; providing a second color die above each first color die, each second color die being separated from each other with a second oxide, bonded to a first color die, and electrically connected to the CMOS wafer through the bonded first color die; removing a portion of each second color die to expose a portion of each bonded first color die; forming a conformal TCO layer over each first and second color die and on a side surface of each second color die and oxide; forming a PECVD oxide layer over the CMOS wafer; and planarizing the PECVD oxide layer.
    Type: Application
    Filed: July 14, 2017
    Publication date: January 17, 2019
    Inventors: Srinivasa BANNA, Deepak NAYAK, Luke ENGLAND, Rahul AGARWAL
  • Publication number: 20190013337
    Abstract: An integrated circuit (IC) microdisplay structure is disclosed. The structure can include: a first oxide layer positioned on a substrate; a first voltage source (VSS) pad within the first oxide layer; a metal pillar disposed within the first oxide layer and on the first VSS pad; a first gallium nitride layer disposed on the metal pillar and extending over the first oxide layer; and at least one subpixel formed from the first gallium nitride layer. Alternatively, the structure can include a first oxide layer positioned on a substrate; a first metal layer positioned on the first oxide layer; a first gallium nitride layer on the first metal layer; and at least one subpixel formed from the first gallium nitride layer. The structure may further include a subpixel driver electrically connected to the at least one subpixels where a portion of the subpixel driver is vertically aligned with a subpixel.
    Type: Application
    Filed: July 5, 2017
    Publication date: January 10, 2019
    Inventors: Deepak K. Nayak, Srinivasa Banna
  • Patent number: 10177178
    Abstract: An integrated circuit (IC) microdisplay structure is disclosed. The structure can include: a first oxide layer positioned on a substrate; a first voltage source (VSS) pad within the first oxide layer; a metal pillar disposed within the first oxide layer and on the first VSS pad; a first gallium nitride layer disposed on the metal pillar and extending over the first oxide layer; and at least one subpixel formed from the first gallium nitride layer. Alternatively, the structure can include a first oxide layer positioned on a substrate; a first metal layer positioned on the first oxide layer; a first gallium nitride layer on the first metal layer; and at least one subpixel formed from the first gallium nitride layer. The structure may further include a subpixel driver electrically connected to the at least one subpixels where a portion of the subpixel driver is vertically aligned with a subpixel.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: January 8, 2019
    Assignee: GLOABLFOUNDRIES INC.
    Inventors: Deepak K. Nayak, Srinivasa Banna
  • Patent number: 10147652
    Abstract: At least one method, apparatus and system disclosed involves a semiconductor substrate on which NMOS and PMOS devices with enhanced current drives may be formed. A first substrate having an enhanced electron mobility is formed. A second substrate having an enhanced hole mobility is formed. The first substrate and the second substrate are bonded for forming a third substrate. A first channel on the third substrate characterized by the enhanced electron mobility is formed. A second channel on the third substrate characterized by the enhanced hole mobility is formed.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: December 4, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Srinivasa Banna
  • Patent number: 10037981
    Abstract: A display system is disclosed. The display system comprises a light emitting diode (LED) device and a backplane (BP) device. The LED device comprises a plurality of LEDs having LED terminals. An LED bonding surface comprising a dielectric layer with LED bonding surface contact pads is coupled to diode terminals of the LEDs. The backplane (BP) device comprises a BP substrate having top and bottom surfaces. A plurality of system on chip (SoC) chips are bonded to chip pads disposed on a bottom surface of the BP device. The SoC chips are electrically coupled to the CMOS components of the BP device and LEDs of the LED device.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: July 31, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Srinivasa Banna, Sanjay Jha, Deepak Nayak, Ajey P. Jacob
  • Publication number: 20180197913
    Abstract: Devices and methods of forming the devices are disclosed. The device includes a substrate and a color LED pixel disposed on the substrate. The color LED pixel includes a red LED, a green LED and a blue LED. Each of the color LED includes a specific color LED body disposed on the respective color region on the substrate, a specific color multiple quantum well (MQW) on the respective color LED body and a specific color top LED layer disposed over the respective color MQW. The MQWs of the red LED, green LED and blue LED includes at least an indium gallium nitride (InxGa1-xN) layer and a gallium nitride (GaN), where x is the atomic percentage of In in the InxGa1-xN layer, and the MQWs of the red LED, green LED and blue LED have different bandgaps by varying x of the InxGa1-xN layer in the red LED, the green LED and the blue LED.
    Type: Application
    Filed: February 21, 2018
    Publication date: July 12, 2018
    Inventors: Srinivasa BANNA, Deepak NAYAK, Ajey P. JACOB
  • Publication number: 20180175107
    Abstract: Disclosed is a device which includes first and second major substrate surfaces. The first substrate surface includes an LED with first and second terminals while the second substrate surface includes CMOS circuit components. The CMOS components and LED are coupled by through silicon via (TSV) contacts which extend through the second substrate surface.
    Type: Application
    Filed: February 20, 2018
    Publication date: June 21, 2018
    Inventors: Deepak NAYAK, Srinivasa BANNA, Ajey P. JACOB