Patents by Inventor Srinivasa Chakravarthy
Srinivasa Chakravarthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240146323Abstract: Methods for operating two or more analog-to-digital converters (ADCs) are presented herein. The method may be implemented in an integrated circuit. The integrated circuit may include a first ADC and a second ADC disposed on a single semiconductor die. The integrated circuit may also include logic circuitry operably coupled to the first and second ADCs. For a digital value obtained by conversion, by the first ADC, of a first analog signal sampled by the first ADC during a period of time overlapping with another period of time during which a second analog signal is being converted by the second ADC, the logic circuitry may be configured to cause the digital value to be marked as noisy.Type: ApplicationFiled: October 28, 2022Publication date: May 2, 2024Inventors: Christy Leigh She, Joonsung Park, Krishnasawamy Nagaraj, Srinivasa Chakravarthy
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Patent number: 11942962Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes interface circuitry to receive an analog signal. The example apparatus also includes sequencer circuitry to: determine whether the apparatus is to operate in a single transfer state or a multiple transfer state; access a configuration from a control register in a plurality of control registers; initiate a conversion of the analog signal to a digital value based on the configuration; and write the digital value to a result register in a plurality of result registers based on the determination.Type: GrantFiled: March 10, 2022Date of Patent: March 26, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Anand Kumar G, Srinivasa Chakravarthy
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Publication number: 20230299778Abstract: Various embodiments disclosed herein relate to adaptive clock signal management, and more specifically to generating a clock signal at desired frequencies based on inputs to a clock subsystem for peripheral use. A clock subsystem is provided herein that comprises an oscillator configured to provide a clock signal at either a first frequency or a second frequency, and a controller coupled to the oscillator and configured to perform various functions. The controller can be configured to determine a desired frequency of the clock signal based on a state of each input of multiple inputs, wherein the multiple inputs comprise a power mode input and an analog-to-digital converter input, and provide a signal to the oscillator to produce the clock signal at the desired frequency.Type: ApplicationFiled: October 31, 2022Publication date: September 21, 2023Inventors: G Anand Kumar, Srinivasa Chakravarthy
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Patent number: 11740106Abstract: In an example, a circuit includes a first comparator, a second comparator, a pulse counter, a processor, a first ADC, and a second ADC. The first comparator has a first input coupled to a first node, a second input, and an output. The second comparator has a first input coupled to a second node, a second input, and an output. A first DAC is coupled to the second input of the first comparator. A second DAC is coupled to the second input of the second comparator. The pulse counter has a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator. The first ADC has an input coupled to the first node and an output coupled to the processor. The second ADC has an input coupled to the second node and an output coupled to the processor.Type: GrantFiled: November 14, 2022Date of Patent: August 29, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Richard Mark Poley, Srinivasa Chakravarthy
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Patent number: 11663095Abstract: A circuit and method for verifying the operation of error checking circuitry. In one example, a circuit includes a memory, a first error checking circuit, a second error checking circuit, and a comparison circuit. The memory includes a data output. The first error checking circuit includes an input and an output. The input of the first error checking circuit is coupled to the data output of the memory. The second error checking circuit includes an input and an output. The input of the second error checking circuit is coupled to the data output of the memory. The comparison circuit includes a first input and a second input. The first input is coupled to the output of the first error checking circuit. The second input is coupled to the output of the second error checking circuit.Type: GrantFiled: July 12, 2021Date of Patent: May 30, 2023Assignee: Texas Instmments IncorporatedInventors: Saya Goud Langadi, Srinivasa Chakravarthy Bs
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Publication number: 20230129042Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes interface circuitry to receive an analog signal. The example apparatus also includes sequencer circuitry to: determine whether the apparatus is to operate in a single transfer state or a multiple transfer state; access a configuration from a control register in a plurality of control registers; initiate a conversion of the analog signal to a digital value based on the configuration; and write the digital value to a result register in a plurality of result registers based on the determination.Type: ApplicationFiled: March 10, 2022Publication date: April 27, 2023Inventors: Anand Kumar G, Srinivasa Chakravarthy
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Publication number: 20230072994Abstract: In an example, a circuit includes a first comparator, a second comparator, a pulse counter, a processor, a first ADC, and a second ADC. The first comparator has a first input coupled to a first node, a second input, and an output. The second comparator has a first input coupled to a second node, a second input, and an output. A first DAC is coupled to the second input of the first comparator. A second DAC is coupled to the second input of the second comparator. The pulse counter has a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator. The first ADC has an input coupled to the first node and an output coupled to the processor. The second ADC has an input coupled to the second node and an output coupled to the processor.Type: ApplicationFiled: November 14, 2022Publication date: March 9, 2023Applicant: Texas Instruments IncorporatedInventors: Richard Mark POLEY, Srinivasa CHAKRAVARTHY
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Patent number: 11540781Abstract: Conventionally, a neuronal controller located inside the central nervous system governing the maintenance of the upright posture of the human body is designed from a control system perspective using proportional-integral-derivative (PID) controllers, wherein human postural sway is modeled either along a sagittal plan or along a frontal plane separately resulting in limited insights on intricacies of a governing neuronal controller. Also, existing neuronal controllers using a reinforcement learning (RL) paradigm are based on complex actor-critic on-policy algorithms. Analyzing human postural sway is critical to detect markers for progression of balance impairments. The present disclosure facilitates modelling the neuronal controller using a simplified RL algorithm, capable of producing postural sway characteristics in both sagittal and frontal plane together.Type: GrantFiled: February 25, 2020Date of Patent: January 3, 2023Assignee: Tata Consultancy Services LimitedInventors: Aniruddha Sinha, Oishee Mazumder, Debatri Chatterjee, Srinivasa Chakravarthy Vaddadi, Dipayan Biswas
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Publication number: 20220416771Abstract: An example apparatus includes multiplexer circuitry configured to couple a communication module to at least one of a data bus input or a test signal; and embedded pattern generator (EPG) circuitry coupled to the multiplexer circuitry, the EPG circuitry including: clock divider circuitry including a plurality of clock outputs, the clock divider circuitry configured to be coupled to an output of a clock, the plurality of clock outputs configured to be of a frequency equal to a division of a frequency of the output of the clock; a multiplexer including a multiplexer output, the multiplexer configured to couple one of the plurality of clock outputs to the multiplexer output; and signal generator circuitry including an input clock, an EPG input, and a plurality of data outputs, the input clock coupled to the multiplexer output, the signal generator circuitry configured to generate a data stream.Type: ApplicationFiled: June 24, 2022Publication date: December 29, 2022Inventors: Srinivasa Chakravarthy, Prasanth Viswanathan Pillai, Mohammed Arif, Bhargov Bora
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Patent number: 11520687Abstract: A system for automating testing of an accessibility screen-reader for a software application includes an accessibility testing module. The accessibility testing module communicates a set of input commands to a user device in which the software application is installed. The set of input commands emulates a set of actions being performed on the software application. For each input command, an audio of a string of utterances is received when the accessibility screen-reader produces the audio. The audio is converted to a text of the string of utterances. The text is compared with a corresponding test string that is expected to be uttered by the accessibility screen-reader when a corresponding action is performed on the software application. If it is determined that the text matches the corresponding test string, it is concluded that the accessibility screen-reader uttered the corresponding test string that was expected to be uttered.Type: GrantFiled: November 20, 2020Date of Patent: December 6, 2022Assignee: Bank of America CorporationInventors: Robert Christopher Coffin, Srinivasa Chakravarthy Kotcherlakota
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Patent number: 11499847Abstract: In an example, a circuit includes a first comparator, a second comparator, a pulse counter, a processor, a first ADC, and a second ADC. The first comparator has a first input coupled to a first node, a second input, and an output. The second comparator has a first input coupled to a second node, a second input, and an output. A first DAC is coupled to the second input of the first comparator. A second DAC is coupled to the second input of the second comparator. The pulse counter has a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator. The first ADC has an input coupled to the first node and an output coupled to the processor. The second ADC has an input coupled to the second node and an output coupled to the processor.Type: GrantFiled: June 23, 2021Date of Patent: November 15, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Richard Mark Poley, Srinivasa Chakravarthy
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Publication number: 20220164278Abstract: A system for automating testing of an accessibility screen-reader for a software application includes an accessibility testing module. The accessibility testing module communicates a set of input commands to a user device in which the software application is installed. The set of input commands emulates a set of actions being performed on the software application. For each input command, an audio of a string of utterances is received when the accessibility screen-reader produces the audio. The audio is converted to a text of the string of utterances. The text is compared with a corresponding test string that is expected to be uttered by the accessibility screen-reader when a corresponding action is performed on the software application. If it is determined that the text matches the corresponding test string, it is concluded that the accessibility screen-reader uttered the corresponding test string that was expected to be uttered.Type: ApplicationFiled: November 20, 2020Publication date: May 26, 2022Inventors: Robert Christopher Coffin, Srinivasa Chakravarthy Kotcherlakota
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Publication number: 20210342233Abstract: A circuit and method for verifying the operation of error checking circuitry. In one example, a circuit includes a memory, a first error checking circuit, a second error checking circuit, and a comparison circuit. The memory includes a data output. The first error checking circuit includes an input and an output. The input of the first error checking circuit is coupled to the data output of the memory. The second error checking circuit includes an input and an output. The input of the second error checking circuit is coupled to the data output of the memory. The comparison circuit includes a first input and a second input. The first input is coupled to the output of the first error checking circuit. The second input is coupled to the output of the second error checking circuit.Type: ApplicationFiled: July 12, 2021Publication date: November 4, 2021Inventors: Saya Goud LANGADI, JR., Srinivasa Chakravarthy BS
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Publication number: 20210318144Abstract: In an example, a circuit includes a first comparator, a second comparator, a pulse counter, a processor, a first ADC, and a second ADC. The first comparator has a first input coupled to a first node, a second input, and an output. The second comparator has a first input coupled to a second node, a second input, and an output. A first DAC is coupled to the second input of the first comparator. A second DAC is coupled to the second input of the second comparator. The pulse counter has a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator. The first ADC has an input coupled to the first node and an output coupled to the processor. The second ADC has an input coupled to the second node and an output coupled to the processor.Type: ApplicationFiled: June 23, 2021Publication date: October 14, 2021Inventors: Richard Mark POLEY, Srinivasa CHAKRAVARTHY
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Patent number: 11073409Abstract: In an example, a circuit includes a first comparator, a second comparator, a pulse counter, a processor, a first ADC, and a second ADC. The first comparator has a first input coupled to a first node, a second input, and an output. The second comparator has a first input coupled to a second node, a second input, and an output. A first DAC is coupled to the second input of the first comparator. A second DAC is coupled to the second input of the second comparator. The pulse counter has a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator. The first ADC has an input coupled to the first node and an output coupled to the processor. The second ADC has an input coupled to the second node and an output coupled to the processor.Type: GrantFiled: December 6, 2018Date of Patent: July 27, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Richard Mark Poley, Srinivasa Chakravarthy
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Patent number: 11061783Abstract: A circuit and method for verifying the operation of error checking circuitry. In one example, a circuit includes a memory, a first error checking circuit, a second error checking circuit, and a comparison circuit. The memory includes a data output. The first error checking circuit includes an input and an output. The input of the first error checking circuit is coupled to the data output of the memory. The second error checking circuit includes an input and an output. The input of the second error checking circuit is coupled to the data output of the memory. The comparison circuit includes a first input and a second input. The first input is coupled to the output of the first error checking circuit. The second input is coupled to the output of the second error checking circuit.Type: GrantFiled: April 29, 2019Date of Patent: July 13, 2021Assignee: Texas Instruments IncorporatedInventors: Saya Goud Langadi, Srinivasa Chakravarthy Bs
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Publication number: 20200341869Abstract: A circuit and method for verifying the operation of error checking circuitry. In one example, a circuit includes a memory, a first error checking circuit, a second error checking circuit, and a comparison circuit. The memory includes a data output. The first error checking circuit includes an input and an output. The input of the first error checking circuit is coupled to the data output of the memory. The second error checking circuit includes an input and an output. The input of the second error checking circuit is coupled to the data output of the memory. The comparison circuit includes a first input and a second input. The first input is coupled to the output of the first error checking circuit. The second input is coupled to the output of the second error checking circuit.Type: ApplicationFiled: April 29, 2019Publication date: October 29, 2020Inventors: Saya Goud LANGADI, Srinivasa Chakravarthy BS
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Publication number: 20200305800Abstract: Conventionally, a neuronal controller located inside the central nervous system governing the maintenance of the upright posture of the human body is designed from a control system perspective using proportional-integral-derivative (PID) controllers, wherein human postural sway is modeled either along a sagittal plan or along a frontal plane separately resulting in limited insights on intricacies of a governing neuronal controller. Also, existing neuronal controllers using a reinforcement learning (RL) paradigm are based on complex actor-critic on-policy algorithms. Analyzing human postural sway is critical to detect markers for progression of balance impairments. The present disclosure facilitates modelling the neuronal controller using a simplified RL algorithm, capable of producing postural sway characteristics in both sagittal and frontal plane together.Type: ApplicationFiled: February 25, 2020Publication date: October 1, 2020Applicant: Tata Consultancy Services LimitedInventors: Aniruddha SINHA, Oishee MAZUMDER, Debatri CHATTERJEE, Srinivasa Chakravarthy VADDADI, Dipayan BISWAS
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Publication number: 20200182656Abstract: In an example, a circuit includes a first comparator, a second comparator, a pulse counter, a processor, a first ADC, and a second ADC. The first comparator has a first input coupled to a first node, a second input, and an output. The second comparator has a first input coupled to a second node, a second input, and an output. A first DAC is coupled to the second input of the first comparator. A second DAC is coupled to the second input of the second comparator. The pulse counter has a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator. The first ADC has an input coupled to the first node and an output coupled to the processor. The second ADC has an input coupled to the second node and an output coupled to the processor.Type: ApplicationFiled: December 6, 2018Publication date: June 11, 2020Inventors: Richard Mark POLEY, Srinivasa CHAKRAVARTHY
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Publication number: 20070288797Abstract: A method generates test vectors for a customer designed integrated circuit having an embedded vendor circuit. The embedded vendor circuit has a proprietary circuit and a nonproprietary circuit. At least one pseudo input is defined to represent a portion of the nonproprietary circuit to emulate the nonproprietary circuit output. An output node of the embedded vendor circuit to which an input of the customer designed circuit is connectable is identified. A test netlist is created which represents circuitry that produces output states at the output node which would be generated by the embedded vendor circuit thereat. The test netlist includes at least one pseudo input and the output node, without including a full netlist of either the proprietary or nonproprietary circuits, and can be used to generate scan test vectors for the customer designed integrated circuit by the automatic test vector generating software program.Type: ApplicationFiled: April 9, 2007Publication date: December 13, 2007Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Srinivasa Chakravarthy, Rubin Parekhji, Julio Hernandez, Kenneth Butler