Patents by Inventor Srinivasa Chakravarthy BS

Srinivasa Chakravarthy BS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Error detection circuit
    Patent number: 11663095
    Abstract: A circuit and method for verifying the operation of error checking circuitry. In one example, a circuit includes a memory, a first error checking circuit, a second error checking circuit, and a comparison circuit. The memory includes a data output. The first error checking circuit includes an input and an output. The input of the first error checking circuit is coupled to the data output of the memory. The second error checking circuit includes an input and an output. The input of the second error checking circuit is coupled to the data output of the memory. The comparison circuit includes a first input and a second input. The first input is coupled to the output of the first error checking circuit. The second input is coupled to the output of the second error checking circuit.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: May 30, 2023
    Assignee: Texas Instmments Incorporated
    Inventors: Saya Goud Langadi, Srinivasa Chakravarthy Bs
  • ERROR DETECTION CIRCUIT
    Publication number: 20210342233
    Abstract: A circuit and method for verifying the operation of error checking circuitry. In one example, a circuit includes a memory, a first error checking circuit, a second error checking circuit, and a comparison circuit. The memory includes a data output. The first error checking circuit includes an input and an output. The input of the first error checking circuit is coupled to the data output of the memory. The second error checking circuit includes an input and an output. The input of the second error checking circuit is coupled to the data output of the memory. The comparison circuit includes a first input and a second input. The first input is coupled to the output of the first error checking circuit. The second input is coupled to the output of the second error checking circuit.
    Type: Application
    Filed: July 12, 2021
    Publication date: November 4, 2021
    Inventors: Saya Goud LANGADI, JR., Srinivasa Chakravarthy BS
  • Error detection circuit
    Patent number: 11061783
    Abstract: A circuit and method for verifying the operation of error checking circuitry. In one example, a circuit includes a memory, a first error checking circuit, a second error checking circuit, and a comparison circuit. The memory includes a data output. The first error checking circuit includes an input and an output. The input of the first error checking circuit is coupled to the data output of the memory. The second error checking circuit includes an input and an output. The input of the second error checking circuit is coupled to the data output of the memory. The comparison circuit includes a first input and a second input. The first input is coupled to the output of the first error checking circuit. The second input is coupled to the output of the second error checking circuit.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: July 13, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Saya Goud Langadi, Srinivasa Chakravarthy Bs
  • ERROR DETECTION CIRCUIT
    Publication number: 20200341869
    Abstract: A circuit and method for verifying the operation of error checking circuitry. In one example, a circuit includes a memory, a first error checking circuit, a second error checking circuit, and a comparison circuit. The memory includes a data output. The first error checking circuit includes an input and an output. The input of the first error checking circuit is coupled to the data output of the memory. The second error checking circuit includes an input and an output. The input of the second error checking circuit is coupled to the data output of the memory. The comparison circuit includes a first input and a second input. The first input is coupled to the output of the first error checking circuit. The second input is coupled to the output of the second error checking circuit.
    Type: Application
    Filed: April 29, 2019
    Publication date: October 29, 2020
    Inventors: Saya Goud LANGADI, Srinivasa Chakravarthy BS