Abstract: A method of coupling an integrated circuit to a substrate includes providing the substrate, forming a contact pad in the substrate, contacting the contact pad with a solder ball, and repeatedly exposing the solder ball to a thermal process to cause intermetallics based on a metal in the contact pad to be formed in the thermal ball.

Abstract: A method of coupling an integrated circuit to a substrate includes providing the substrate, forming a contact pad in the substrate, contacting the contact pad with a solder ball, and repeatedly exposing the solder ball to a thermal process to cause intermetallics based on a metal in the contact pad to be formed in the thermal ball.

Abstract: A multilayer ceramic substrate in which an outer metal pad is anchored to the substrate by a single metal-filled via in the first ceramic layer adjacent to the metal pad. In turn, this single metal-filled via is anchored to the substrate by a larger, single metal-filled via in the next ceramic layer adjacent to the first ceramic layer. Preferably, the metal-filled vias and metal pad are 100 volume percent metal.

Abstract: A process for fabricating a structure using a metal carrier and forming a double capacitor structure. The process comprises forming a first via hole through the metal carrier, forming a dielectric layer around the metal carrier and inside the first via hole, forming a second via hole through the dielectric layer and the metal carrier, and filling at least one of the via holes with conductive material. In one preferred embodiment, the process further comprises forming a third via hole through the metal carrier before the forming of a dielectric layer, wherein the dielectric layer is formed around the metal carrier, inside the first via hole, and inside the third via hole. The first via hole, the second via hole, and the third via hole are all filled with a conductive material. In one preferred embodiment, the dielectric layer comprises a top surface opposed to a bottom surface, and electrodes are formed on at least one of the top surface and the bottom surface of the dielectric layer.

Abstract: A brazing method for the direct bonding of a metallic item to a refractory metal without the need for an adhesion layer. The direct brazing process uses a Cu--Ag--Ni alloy which eliminates the need for the steps of plating a refractory metal to be bonded to a metallic material with a nickel layer (or other nickel-containing adhesion layer) and diffusion annealing the plated refractory metal prior to brazing. The brazed joint produced by the direct brazing method between a refractory metal and a metallic item has a substantially reduced layer of nickel in the as-brazed joint which improves the mechanical properties of the joint.

Abstract: A ceramic substrate pad used for establishing brazed connection between a pin and the substrate in the packaging of microelectronic semiconductor circuit chip. The pad is characterized by a stepped setback in the upper surface thereof which setback is oxidized to prevent wetting by the brazing alloy which bonds the pin to the pad. Stresses attributable to the brazing are isolated from the setback area and thus have reduced effect in causing cracking at the edges of the pad-substrate interface.

Abstract: A method for co-sintering ceramic/metal multi-layered ceramic substrates wherein X-Y shrinkage is controlled and X-Y distortion and Z-direction chamber are substantially eliminated. Binder-burnoff is substantially not aggravated during this process as well. The process is accomplished by applying selective forces to the surfaces of the ceramic substrates to control lateral movement while allowing Z direction shrinkage movement. Frictional force means, pneumatic forced means and weights are among the means used to supply forces. Cerium oxide is used in certain embodiments to enhance binder-burnoff.

Abstract: A multilayered ceramic (MLC) substrate having embedded and exposed conductors suitable for mounting and interconnecting a plurality of electronic devices exterior thereof. The horizontal planar conductors comprise substantially a plurality of solid, non-porous, homogeneous metal patterns, whereas the vertical interplanar connection conductors are substantially porous metal conductors that are formed by methods such as screening. The process to form the MLC substrate involves forming a pattern of solid, nonporous conductors to a backing sheet having a release layer, then transferring the pattern to a ceramic green sheet. Zero X-Y shrinkage sintering processes allow the MLC substrate and solid metal conductors to be densified without distortion of the solid metal patterns or the ceramic.

Abstract: A multilayered ceramic (MLC) substrate having embedded and exposed conductors suitable for mounting and interconnecting a plurality of electronic devices exterior thereof. The horizontal planar conductors comprise substantially a plurality of solid, non-porous, homogeneous metal patterns, whereas the vertical interplanar connection conductors are substantially porous metal conductors that are formed by methods such as screening. The process to form the MLC substrate involves forming a pattern of solid, nonporous conductors to a backing sheet having a release layer, then transferring the pattern to a ceramic green sheet. Zero X-Y shrinkage sintering processes allow the MLC substrate and solid metal conductors to be densified without distortion of the solid metal patterns or the ceramic.