Patents by Inventor Srinivasa R. Arikati

Srinivasa R. Arikati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Cell overlap violation diagnostics with machine learning
    Patent number: 12008303
    Abstract: A method for identifying design rule checking (DRC) violation types within an integrated circuit (IC) chip design includes receiving an IC chip design layout, and performing a DRC process on the IC chip design layout to identify DRC violations. Further, the method includes generating clustered heatmaps from heatmaps generated from the DRC violations. The method further includes identifying a first DRC violation type and a corresponding first cell pair within the IC chip design layout by analyzing the clustered heatmaps with a diagnostic model.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: June 11, 2024
    Assignee: Synopsys, Inc.
    Inventors: Leslie K. Hwang, Srinivasa R. Arikati
  • CELL OVERLAP VIOLATION DIAGNOSTICS WITH MACHINE LEARNING
    Publication number: 20220067265
    Abstract: A method for identifying design rule checking (DRC) violation types within an integrated circuit (IC) chip design includes receiving an IC chip design layout, and performing a DRC process on the IC chip design layout to identify DRC violations. Further, the method includes generating clustered heatmaps from heatmaps generated from the DRC violations. The method further includes identifying a first DRC violation type and a corresponding first cell pair within the IC chip design layout by analyzing the clustered heatmaps with a diagnostic model.
    Type: Application
    Filed: August 25, 2021
    Publication date: March 3, 2022
    Inventors: Leslie K. HWANG, Srinivasa R. ARIKATI
  • Detecting and displaying multi-patterning fix guidance
    Patent number: 10902176
    Abstract: A computer implemented method for validating a design is presented. The method includes generating, using the computer, a graph non-decomposable to a colored graph representative of the design, when the computer is invoked to validate the design. The method further includes identifying, using the computer, at least one guidance to at least one conflict in a mask layout associated with the design, the conflict causing the graph to be non-decomposable.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: January 26, 2021
    Assignee: Synopsys, Inc.
    Inventors: Erdem Cilingir, Srinivasa R Arikati, Weiping Fang, Marco Hug
  • DETECTING AND DISPLAYING MULTI-PATTERNING FIX GUIDANCE
    Publication number: 20170004251
    Abstract: A computer implemented method for validating a design is presented. The method includes generating, using the computer, a graph non-decomposable to a colored graph representative of the design, when the computer is invoked to validate the design. The method further includes identifying, using the computer, at least one guidance to at least one conflict in a mask layout associated with the design, the conflict causing the graph to be non-decomposable.
    Type: Application
    Filed: June 10, 2016
    Publication date: January 5, 2017
    Inventors: Erdem Cilingir, Srinivasa R. Arikati, Weiping Fang, Marco Hug