Patents by Inventor Srinivasa R. Banna
Srinivasa R. Banna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10355043Abstract: The present disclosure relates to semiconductor structures and, more particularly, to integrated vertical transistors and light emitting diodes and methods of manufacture. The structure includes a vertically oriented stack of material having a light emitting diode (LED) integrated with a source region and a drain region of a vertically oriented active device.Type: GrantFiled: June 28, 2017Date of Patent: July 16, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Ajey P. Jacob, Deepak K. Nayak, Srinivasa R. Banna
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Patent number: 10217900Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to light emitting diode (LED) structures and methods of manufacture. The method includes: forming a buffer layer on a substrate, the buffer layer having at least a lattice mismatch with the substrate; and relaxing the buffer layer by pixelating the buffer layer into discrete islands, prior to formation of a quantum well.Type: GrantFiled: July 6, 2017Date of Patent: February 26, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Deepak K. Nayak, Srinivasa R. Banna, Ajey P. Jacob
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Publication number: 20190058082Abstract: The present disclosure relates to semiconductor structures and, more particularly, to uniform semiconductor nanowire and nanosheet light emitting diodes and methods of manufacture. The structure includes a buffer layer; at least one dielectric layer on the buffer layer, the at least one dielectric layer having a plurality of openings exposing the buffer layer; and a plurality of uniformly sized and shaped nanowires or nanosheets formed in the openings and extending above the at least one dielectric layer.Type: ApplicationFiled: August 16, 2017Publication date: February 21, 2019Inventors: Deepak K. NAYAK, Srinivasa R. BANNA, Ajey P. JACOB
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Publication number: 20190013436Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to light emitting diode (LED) structures and methods of manufacture. The method includes: forming a buffer layer on a substrate, the buffer layer having at least a lattice mismatch with the substrate; and relaxing the buffer layer by pixelating the buffer layer into discrete islands, prior to formation of a quantum well.Type: ApplicationFiled: July 6, 2017Publication date: January 10, 2019Inventors: Deepak K. NAYAK, Srinivasa R. BANNA, Ajey P. JACOB
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Publication number: 20190006413Abstract: The present disclosure relates to semiconductor structures and, more particularly, to integrated vertical transistors and light emitting diodes and methods of manufacture. The structure includes a vertically oriented stack of material having a light emitting diode (LED) integrated with a source region and a drain region of a vertically oriented active device.Type: ApplicationFiled: June 28, 2017Publication date: January 3, 2019Inventors: Ajey P. JACOB, Deepak K. NAYAK, Srinivasa R. BANNA
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Patent number: 10056453Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor wafers with reduced bowing and warping and methods of manufacture. The structure includes a substrate including plurality of trenches which have progressively different depths as they extend radially inwardly from an edge of the substrate towards a center of the substrate.Type: GrantFiled: July 22, 2016Date of Patent: August 21, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Ajey Poovannummoottil Jacob, Srinivasa R. Banna, Deepak K. Nayak, Bartlomiej J. Pawlak
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Publication number: 20180026096Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor wafers with reduced bowing and warping and methods of manufacture. The structure includes a substrate including plurality of trenches which have progressively different depths as they extend radially inwardly from an edge of the substrate towards a center of the substrate.Type: ApplicationFiled: July 22, 2016Publication date: January 25, 2018Inventors: Ajey Poovannummoottil Jacob, Srinivasa R. Banna, Deepak K. Nayak, Bartlomiej J. Pawlak
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Publication number: 20170077234Abstract: Devices and methods of creating elastic relaxation of epitaxially grown lattice mismatched films for semiconductor devices are provided. One method includes, for instance: obtaining a wafer including a substrate; epitaxially growing at least one first silicon germanium (SiGe) layer over the wafer; and epitaxially growing at least one second SiGe layer over the at least one first SiGe layer. One device includes, for instance: a wafer including a substrate; at least one first layer of semiconductor material disposed over the wafer; at least one second layer of semiconductor material disposed over the at least one first layer of semiconductor material; and at least one first and second openings, each opening extending through the at least one second layer of semiconductor material, the at least one first layer of semiconductor material, and a portion of the substrate.Type: ApplicationFiled: September 14, 2015Publication date: March 16, 2017Applicant: GLOBALFOUNDRIES Inc.Inventors: Neeraj TRIPATHI, Srinivasa R. BANNA
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Patent number: 9524971Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.Type: GrantFiled: February 5, 2015Date of Patent: December 20, 2016Inventors: Srinivasa R. Banna, Michael A. van Buskirk, Timothy Thurgate
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Patent number: 9263133Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns, each memory cell. Each of the memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a gate region and disposed between the first region and the second region, wherein the body region may include a plurality of floating body regions and a plurality of floating gate regions capacitively coupled to the at least one word line.Type: GrantFiled: August 30, 2013Date of Patent: February 16, 2016Assignee: MICRON TECHNOLOGY, INC.Inventors: Srinivasa R. Banna, Michael A. Van Bushkirk, Timothy Thurgate
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Publication number: 20150155285Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.Type: ApplicationFiled: February 5, 2015Publication date: June 4, 2015Applicant: Micron Technology, Inc.Inventors: Srinivasa R. BANNA, Michael A. VAN BUSKIRK, Timothy THURGATE
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Patent number: 9019759Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.Type: GrantFiled: October 1, 2013Date of Patent: April 28, 2015Assignee: Micron Technology, Inc.Inventors: Srinivasa R. Banna, Michael A. Van Buskirk, Timothy Thurgate
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Patent number: 8982633Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region connected to a bit line extending in a first orientation and a second region connected to a source line extending in a second orientation. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line extending in the second orientation, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region connected to a carrier injection line extending in the second orientation, wherein the first region, the second region, the body region, and the third region are disposed in sequential contiguous relationship.Type: GrantFiled: July 30, 2013Date of Patent: March 17, 2015Assignee: Micron Technology, Inc.Inventors: Srinivasa R. Banna, Michael A. Van Buskirk
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Publication number: 20140029360Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.Type: ApplicationFiled: October 1, 2013Publication date: January 30, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Srinivasa R. BANNA, Michael A. VAN BUSKIRK, Timothy THURGATE
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Publication number: 20140003144Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns, each memory cell. Each of the memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a gate region and disposed between the first region and the second region, wherein the body region may include a plurality of floating body regions and a plurality of floating gate regions capacitively coupled to the at least one word line.Type: ApplicationFiled: August 30, 2013Publication date: January 2, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Srinivasa R. BANNA, Michael A. VAN BUSKIRK, Timothy THURGATE
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Publication number: 20130315000Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region connected to a bit line extending in a first orientation and a second region connected to a source line extending in a second orientation. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line extending in the second orientation, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region connected to a carrier injection line extending in the second orientation, wherein the first region, the second region, the body region, and the third region are disposed in sequential contiguous relationship.Type: ApplicationFiled: July 30, 2013Publication date: November 28, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Srinivasa R. BANNA, Michael A. VAN BUSKIRK
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Patent number: 8264017Abstract: A junction field effect transistor includes a channel region, a gate region coupled to the channel region, a well tap region coupled to the gate region and the channel region, and a well region coupled to the well tap region and the channel region. A double gate operation is achieved by this structure as a voltage applied to the gate region is also applied to the well region through the well tap region in order to open the channel from both the gate region and the well region.Type: GrantFiled: August 26, 2011Date of Patent: September 11, 2012Assignee: SuVolta, Inc.Inventor: Srinivasa R. Banna
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Publication number: 20110303955Abstract: A junction field effect transistor includes a channel region, a gate region coupled to the channel region, a well tap region coupled to the gate region and the channel region, and a well region coupled to the well tap region and the channel region. A double gate operation is achieved by this structure as a voltage applied to the gate region is also applied to the well region through the well tap region in order to open the channel from both the gate region and the well region.Type: ApplicationFiled: August 26, 2011Publication date: December 15, 2011Applicant: SuVolta, Inc.Inventor: Srinivasa R. Banna
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Patent number: 8017998Abstract: Gettering contaminants for formation of integrated circuits on a semiconductor-on-insulator structure is described. A semiconductor-on-insulator structure is configured to attract contaminants. Contaminant attractor regions are formed using ion implantation into a semiconductor layer of the semiconductor-on-insulator structure. The semiconductor layer is located above a buried insulator layer of the semiconductor-on-insulator structure. The contaminant attractor regions are spaced away from active regions. Tiles are located on an upper surface of the buried insulator layer. The contaminant attractor regions are formed adjacent to, in close proximity to, or in the tiles. At least one dielectric layer laterally adjacent to the tiles and is disposed on the upper surface of the buried insulator layer. The at least one dielectric layer at least inhibits lateral migration of contaminants to the active regions.Type: GrantFiled: September 8, 2009Date of Patent: September 13, 2011Assignee: T-RAM Semiconductor, Inc.Inventors: Srinivasa R. Banna, Scott Robins
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Patent number: 8017476Abstract: A junction field effect transistor includes a channel region, a gate region coupled to the channel region, a well tap region coupled to the gate region and the channel region, and a well region coupled to the well tap region and the channel region. A double gate operation is achieved by this structure as a voltage applied to the gate region is also applied to the well region through the well tap region in order to open the channel from both the gate region and the well region.Type: GrantFiled: December 2, 2008Date of Patent: September 13, 2011Assignee: SuVolta, Inc.Inventor: Srinivasa R. Banna