Abstract: A system includes a switching converter, an input voltage source coupled to an input of the switching converter, and a load coupled to an output of the switching converter. The system also includes a load sense circuit coupled to the load and configured to provide a load sense signal. The system also includes an oscillator coupled to the switching converter and configured to provide a spread spectrum modulated (SSM) clock signal to the switching converter, wherein a frequency of the SSM clock signal varies as a function of the load sense signal.

Abstract: A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

Abstract: A system includes a switching converter, an input voltage source coupled to an input of the switching converter, and a load coupled to an output of the switching converter. The system also includes a load sense circuit coupled to the load and configured to provide a load sense signal. The system also includes an oscillator coupled to the switching converter and configured to provide a spread spectrum modulated (SSM) clock signal to the switching converter, wherein a frequency of the SSM clock signal varies as a function of the load sense signal.

Abstract: A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

Abstract: A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

Abstract: A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

Abstract: A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

Abstract: The present disclosure relates to a reconfigurable multicore inductor capacitor (LC) oscillator comprising a plurality of oscillator cores. The oscillator may be configured at run-time, at manufacturing, or at production, which may allow for the tailoring of operating characteristics of the oscillator, such as phase noise, electromagnetic interference, or power consumption, for a specific application after production. The cores are coupled through an interconnect network to a common electrical signal output. A subset of the cores may be selectively enabled while the remainder of the cores is disabled. The ability to enable only a subset of the cores allows the total number of enabled cores to be reconfigurable. Furthermore, the direction in which oscillation current flows through the inductor of the cores may be configured. Reconfiguring the number of enabled cores and/or the oscillation current direction in the cores allow operating characteristics of the oscillator to be tailored after production.

Abstract: A method for secure payment transactions over a network between a support help desk computing system and a customer computing system is provided. The method includes establishing a chat session between the help desk and the customer using a chat application program; receiving a purchase order from the customer; communicating a unique URL payment link to the customer, wherein the URL payment link is configured for allowing the customer to establish communication with an order processing system to provide sensitive payment information to the order processing system; receiving the sensitive payment information at the order processing system communicated from the customer; encrypting the sensitive payment information; providing the encrypted sensitive payment information to the help desk, wherein the encrypted sensitive payment information is displayed in a masked format on a display of the help desk; and completing the purchase order using the encrypted sensitive payment information.

Abstract: Methods and systems are provided for adaptively configuring voltage-controlled oscillator (VCO) arrays, such as to reduce mismatches among the VCOs. A plurality of voltage-controlled oscillators (VCOs), connected in parallel to a common control input, and with each VCO outputting an oscillating signal based on the common control input and an adjustment input, may be configured to reduce mismatches among the VCOs. The plurality of VCO may be configured by adjusting at least one operational parameter applicable to interconnection paths connecting outputs of the plurality of VCOs; measuring a mismatch between signals at the outputs of the plurality of VCOs with respect to a first signal parameter; and adjusting a first operational parameter applicable to one or more of the plurality of VCOs to reduce mismatch between signals at the outputs of the plurality of VCOs with respect to a first signal parameter.

Abstract: Method and systems are provided for voltage-controlling and tuning of oscillators. An example system may include a signal source that provides an input signal for generating oscillations and a frequency tuning network for tuning frequency of the oscillations. The frequency tuning network may include one or more input circuits configured for receiving the input signal from the signal source, and a plurality of capacitors. The frequency tuning network may be configured to tune the frequency of the oscillations by adjusting at least one parameter or function applicable to capacitance within the frequency tuning network and/or within other components of the system. The frequency tuning network may be configured to tune the frequency of the oscillations by adjusting amplifying of capacitance. Adjusting amplifying of capacitance in the system may include inhibiting amplifying of at least one capacitor within at least one other component of the system.

Abstract: Method and systems are provided for voltage-controlling and tuning of oscillators. An oscillator may comprise comprises an oscillator core configured for contributing gain to oscillations generated in the oscillator and a frequency tuning network connected between the oscillator core and a signal source that provides an input signal for creating the oscillations in the oscillator. The frequency tuning network may be configured for tuning frequency of the oscillations, to inhibit amplifying a first capacitance from the oscillator core and to amplify a second capacitance from the frequency tuning network. The frequency of oscillations may be tuned by varying a capacitance, and isolating one or more of noise sources or parasitic capacitances from the tuning network.

Abstract: A method for secure payment transactions over a network between a support help desk computing system and a customer computing system is provided. The method includes establishing a chat session between the help desk and the customer using a chat application program; receiving a purchase order from the customer; communicating a unique URL payment link to the customer, wherein the URL payment link is configured for allowing the customer to establish communication with an order processing system to provide sensitive payment information to the order processing system; receiving the sensitive payment information at the order processing system communicated from the customer; encrypting the sensitive payment information; providing the encrypted sensitive payment information to the help desk, wherein the encrypted sensitive payment information is displayed in a masked format on a display of the help desk; and completing the purchase order using the encrypted sensitive payment information.

Abstract: Methods and systems are provided for adaptively configuring voltage-controlled oscillator (VCO) arrays, such as to reduce mismatches among the VCOs. A plurality of voltage-controlled oscillators (VCOs), connected in parallel to a common control input, and with each VCO outputting an oscillating signal based on the common control input and an adjustment input, may be configured to reduce mismatches among the VCOs. The plurality of VCO may be configured by adjusting at least one operational parameter applicable to interconnection paths connecting outputs of the plurality of VCOs; measuring a mismatch between signals at the outputs of the plurality of VCOs with respect to a first signal parameter; and adjusting a first operational parameter applicable to one or more of the plurality of VCOs to reduce mismatch between signals at the outputs of the plurality of VCOs with respect to a first signal parameter.

Abstract: A method for secure payment transactions over a network between a support help desk computing system and a customer computing system is provided. The method includes establishing a chat session between the help desk and the customer using a chat application program; receiving a purchase order from the customer; communicating a unique URL payment link to the customer, wherein the URL payment link is configured for allowing the customer to establish communication with an order processing system to provide sensitive payment information to the order processing system; receiving the sensitive payment information at the order processing system communicated from the customer; encrypting the sensitive payment information; providing the encrypted sensitive payment information to the help desk, wherein the encrypted sensitive payment information is displayed in a masked format on a display of the help desk; and completing the purchase order using the encrypted sensitive payment information.

Abstract: The present disclosure relates to a reconfigurable multicore inductor capacitor (LC) oscillator comprising a plurality of oscillator cores. The oscillator may be configured at run-time, at manufacturing, or at production, which may allow for the tailoring of operating characteristics of the oscillator, such as phase noise, electromagnetic interference, or power consumption, for a specific application after production. The cores are coupled through an interconnect network to a common electrical signal output. A subset of the cores may be selectively enabled while the remainder of the cores is disabled. The ability to enable only a subset of the cores allows the total number of enabled cores to be reconfigurable. Furthermore, the direction in which oscillation current flows through the inductor of the cores may be configured. Reconfiguring the number of enabled cores and/or the oscillation current direction in the cores allow operating characteristics of the oscillator to be tailored after production.

Abstract: A method and system are provided for reducing mismatch between oscillators in an LC VCO array. In an implementation, a method comprises measuring the mismatch between the driver strengths, by measuring the corresponding oscillation amplitudes, and a mismatch between the resonance frequency of each LC VCO in the array of VCOs, and adjusting each LC VCO to reduce the measured amplitude and frequency mismatches. In an implementation, the measuring and adjusting is performed once to calibrate the array of VCOs. In another implementation, the system measures and adjusts the array of VCOs repeatedly. In another implementation, the LC VCO array has a master VCO and a plurality of slave VCOs connected to the master VCO by slave PLLs to reduce phase noise caused by mismatches.

Abstract: Methods and systems are provided for generating balanced oscillations in oscillators. An oscillator comprises a resonator input configured to receive, from an electro-mechanical resonator, a resonator signal; and an oscillator core comprising a first and a second complementary inverters forming a first loop and a second loop with the resonator input, respectively. The inverters are programmable to contribute to the resonator signal a first gain or a second gain to generate balanced oscillations in the oscillator, with the first gain being less than an upper threshold gain required to generate parasitic-mode oscillations when starting balanced oscillations, and the second gain being equal to or greater than a lower threshold, gain required to generate resonator-mode oscillations. Each inverter is configured to regulate gain contributed by the inventor based on regulating amount of power received to control the gain.

Abstract: Method and systems are provided for voltage-controlling and tuning of oscillators. An oscillator may comprise comprises an oscillator core configured for contributing gain to oscillations generated in the oscillator and a frequency tuning network connected between the oscillator core and a signal source that provides an input signal for creating the oscillations in the oscillator. The frequency tuning network may be configured for tuning frequency of the oscillations, to inhibit amplifying a first capacitance from the oscillator core and to amplify a second capacitance from the frequency tuning network. The frequency of oscillations may be tuned by varying a capacitance, and isolating one or more of noise sources or parasitic capacitances from the tuning network.

Abstract: A cross-coupled complementary balanced electro-mechanical oscillator and a method for generating balanced oscillations. The oscillator comprises an electro-mechanical resonator connected to an oscillator core. The oscillator core comprises capacitively cross-coupled complementary programmable inverters and a resistor network. The capacitors inhibit the inverters from latching to a non-oscillatory direct-current (DC) state. The resistor network forms a high pass filter with the capacitors to inhibit relaxation oscillations. The inverters are programmable such that their gain can be varied over time to avoid parasitic oscillations. The oscillator may be frequency-tunable. The method comprises starting balanced oscillations in the oscillator with a low gain to inhibit high-frequency parasitic oscillation modes, inhibiting latching to a DC state using a capacitance, and inhibiting relaxation oscillations using a high pass filter, and varying gain over time to improve phase noise performance.