Abstract: A communications system may include at least a first user equipment (UE) device and a second UE device that communicate with one or more hosts via a cellular network and a call routing server. The first UE and the second UE may be paired and may convey peer-to-peer (P2P) signals between each other when in close proximity. The first UE may communicate with the cellular network using a Mobile Station International Subscriber Directory Number (MSISDN). The MSISDN may, as one example, be shared between the first UE and the second UE. In response to a trigger condition associated with the second UE moving out of proximity to the first UE and/or a user input, communication with the cellular network using the MSISDN may switch from the first UE to the second UE. This may be reversed when the second UE moves back into proximity to the first UE.

Abstract: Process inserts, assemblies, and related methods for use in monitoring high velocity fluids or supporting instruments that monitor and manage high velocity fluids are disclosed. Exemplary inserts include a head having a cavity for receiving an instrument, a shank, and an integral flange. The shank includes an elongated body having a first end disposed proximate to the head, a free end opposite the first end, and a threaded portion spaced apart from the first and free ends. Exemplary process insert assemblies include a process insert having a shank and a threaded support disposed around the shank. Methods of making and using process inserts are also disclosed. For example, a method of installing a process insert on a container includes inserting the free end of the process insert in the interior volume of a container containing a high velocity fluid.

Abstract: A controller includes a first modulator configured to generate a first control signal having an enable state at a first time, based at least in part on an output voltage of a power converter including a first half-bridge power stage and a second half-bridge power stage. The enable state of the first control signal causes a first transistor of the first half-bridge power stage to be turned on. The controller further includes a detector configured to detect a second time occurring subsequent to the first time, based on a current provided at a switching terminal of the second half-bridge power stage. The controller also includes a second modulator configured to generate a second control signal having an enable state at the second time, wherein the enable state of the second control signal causes a second transistor of the second half-bridge power stage to be turned on.

Abstract: Process inserts, assemblies, and related methods for use in monitoring high velocity fluids or supporting instruments that monitor and manage high velocity fluids are disclosed. Exemplary inserts include a head having a cavity for receiving an instrument, a shank, and an integral flange. The shank includes an elongated body having a first end disposed proximate to the head, a free end opposite the first end, and a threaded portion spaced apart from the first and free ends. Exemplary process insert assemblies include a process insert having a shank and a threaded support disposed around the shank. Methods of making and using process inserts are also disclosed. For example, a method of installing a process insert on a container includes inserting the free end of the process insert in the interior volume of a container containing a high velocity fluid.

Abstract: Process inserts, assemblies, and related methods for use in monitoring high velocity fluids or supporting instruments that monitor and manage high velocity fluids are disclosed. Exemplary inserts include a head having a cavity for receiving an instrument, a shank, and an integral flange. The shank includes an elongated body having a first end disposed proximate to the head, a free end opposite the first end, and a threaded portion spaced apart from the first and free ends. Exemplary process insert assemblies include a process insert having a shank and a threaded support disposed around the shank. Methods of making and using process inserts are also disclosed. For example, a method of installing a process insert on a container includes inserting the free end of the process insert in the interior volume of a container containing a high velocity fluid.

Abstract: Process inserts, assemblies, and related methods for use in monitoring high velocity fluids or supporting instruments that monitor and manage high velocity fluids are disclosed. Exemplary inserts include a head having a cavity for receiving an instrument, a shank, and a hub. The shank includes an elongated body having a first end disposed proximate to the head, a free end opposite the first end, and a threaded portion spaced apart from the first and free ends. The hub can form a lapped joint. Exemplary process insert assemblies include a process insert having a shank and a threaded support disposed around the shank. Methods of making and using process inserts are also disclosed. For example, a method of installing a process insert on a container includes inserting the free end of the process insert in the interior volume of a container containing a high velocity fluid.

Abstract: A system and method are described for providing hints to a processing unit that subsequent operations are likely. Responsively, the processing unit takes steps to prepare for the likely subsequent operations. Where the hints are more likely than not to be correct, the processing unit operates more efficiently. For example, in an embodiment, the processing unit consumes less power. In another embodiment, subsequent operations are performed more quickly because the processing unit is prepared to efficiently handle the subsequent operations.

Abstract: Process inserts, assemblies, and related methods for use in monitoring high velocity fluids or supporting instruments that monitor and manage high velocity fluids are disclosed. Exemplary inserts include a head having a cavity for receiving an instrument, a shank, and an integral flange. The shank includes an elongated body having a first end disposed proximate to the head, a free end opposite the first end, and a threaded portion spaced apart from the first and free ends. Exemplary process insert assemblies include a process insert having a shank and a threaded support disposed around the shank. Methods of making and using process inserts are also disclosed. For example, a method of installing a process insert on a container includes inserting the free end of the process insert in the interior volume of a container containing a high velocity fluid.

Abstract: Process inserts, assemblies, and related methods for use in monitoring high velocity fluids or supporting instruments that monitor and manage high velocity fluids are disclosed. Exemplary inserts include a head having a cavity for receiving an instrument, a shank, and a hub. The shank includes an elongated body having a first end disposed proximate to the head, a free end opposite the first end, and a threaded portion spaced apart from the first and free ends. The hub can form a lapped joint. Exemplary process insert assemblies include a process insert having a shank and a threaded support disposed around the shank. Methods of making and using process inserts are also disclosed. For example, a method of installing a process insert on a container includes inserting the free end of the process insert in the interior volume of a container containing a high velocity fluid.

Abstract: This invention relates to a process for preparation of biodegradable biocompostable biodigestible PEPlene polymer (polyolefins) comprising steps of: Mixing at least one peptide with at least one protein and enzyme, Adding a composting agent, Blending with at least one polymer in presence of additive to obtain said PEPlene polymer (polyolefins) material.

Abstract: An approach is provided for enabling power reduction in floating-point operations. In one example, a system receives floating-point numbers of a fused multiply-add instruction. The system determines the fused multiply-add instruction does not require compliance with a standard of precision for floating-point numbers. The system generates gating signals for an integrated circuit that is configured to perform operations of the fused multiply-add instruction. The system then sends the gating signals to the integrated circuit to turn off a plurality of logic gates included in the integrated circuit.

Abstract: This invention relates to a process for preparation of biodegradable biocompostable biodigestible PEPlene polymer comprising steps of: Mixing at least one peptide with at least one protein and enzyme, Adding a composting agent, Blending with at least one polymer in presence of additive to obtain said PEPlene polymer material.

Abstract: One embodiment of the present invention includes a method for performing arithmetic operations on arbitrary width integers using fixed width elements. The method includes receiving a plurality of input operands, segmenting each input operand into multiple sectors, performing a plurality of multiply-add operations based on the multiple sectors to generate a plurality of multiply-add operation results, and combining the multiply-add operation results to generate a final result. One advantage of the disclosed embodiments is that, by using a common fused floating point multiply-add unit to perform arithmetic operations on integers of arbitrary width, the method avoids the area and power penalty of having additional dedicated integer units.

Abstract: A system and method are provided for performing 32-bit or dual 16-bit floating-point arithmetic operations using logic circuitry. An operating mode that specifies an operating mode for a multiplication operation is received, where the operating mode is one of a 32-bit floating-point mode and a dual 16-bit floating-point mode. Based on the operating mode, nine recoding terms for a mantissa of at least one floating-point input operand are determined. A dual-mode multiplier array circuit that is configurable to generate partial products for either one 32-bit floating-point result or for two 16-bit floating-point results computes the partial products based on the nine recoding terms. The partial products are processed to generate an output based on the operating mode.

Abstract: A fused floating-point multiply-add element includes a multiplier that generates a product, and a shifter that shifts an addend within a narrow range. Interpreting logic analyzes the magnitude of the addend relative to the product and then causes logic arrays to position the shifted addend within the left, center, or right portions of a composite register depending in the magnitude of the addend relative to the product. The interpreting logic also forces other portions of the composite register to zero. When the addend is zero, the interpreting logic forces all portions of the composite register to zero. Final combining logic then adds the contents of the composite register to the product.

Abstract: A system and method are provided for dynamically reducing power consumption of floating-point logic. A disable control signal that is based on a characteristic of a floating-point format input operand is received and a portion of a logic circuit is disabled based on the disable control signal. The logic circuit processes the floating-point format input operand to generate an output.

Abstract: A tenant provisioning system. The system allows users to request creation of test tenants for a multi-tenant service targeting specific infrastructure resources and automated bulk creation of test tenants. Test tenants created by the system are clearly identified as test tenants to prevent test tenants from being misreported by business intelligence systems providing information about the multi-tenant service. Automated provisioning of test tenants on a regular schedule provides a mechanism for monitoring the operation of the multi-tenant service. Further, the ability to provision a test tenant in specific infrastructure resources allows comprehensive operational testing of most or all infrastructure resources, as well as targeted testing of individual infrastructure resources. The system may provide test tenants with an expiration allowing automatic removal of out-of-date test tenants. The system reduces the costs and errors inherent with the manual creation of test tenants.

Abstract: A shared account service may be provided to consolidate account creation for one or more service providers. A unified UI is provided to receive a description information of one or more accounts of a tenant. A contract is configured with a service provider based on an analysis of the description information received through the unified UI and a capability information of the service provider. The contract is transmitted to the service provider to cause the service provider to create the account.

Abstract: A system and method are provided for performing 32-bit or dual 16-bit floating-point arithmetic operations using logic circuitry. An operating mode that specifies an operating mode for a multiplication operation is received, where the operating mode is one of a 32-bit floating-point mode and a dual 16-bit floating-point mode. Based on the operating mode, nine recoding terms for a mantissa of at least one floating-point input operand are determined. A dual-mode multiplier array circuit that is configurable to generate partial products for either one 32-bit floating-point result or for two 16-bit floating-point results computes the partial products based on the nine recoding terms. The partial products are processed to generate an output based on the operating mode.

Abstract: A fused floating-point multiply-add element includes a multiplier that generates a product, and a shifter that shifts an addend within a narrow range. Interpreting logic analyzes the magnitude of the addend relative to the product and then causes logic arrays to position the shifted addend within the left, center, or right portions of a composite register depending in the magnitude of the addend relative to the product. The interpreting logic also forces other portions of the composite register to zero. When the addend is zero, the interpreting logic forces all portions of the composite register to zero. Final combining logic then adds the contents of the composite register to the product.