Abstract: A hard disk drive has disks with data sector preambles that allow for inter-track interference. The same data sector preamble is used for all data sectors in a track but the preamble in each track is different from the preamble in radially adjacent tracks. In a first embodiment each preamble includes a synchronization field (SF) and synchronization mark (SM) that are the same in each track but different from the SF and SM in radially adjacent tracks. Only two unique SFs and two unique SMs are required, with the two SFs and two SMs alternating in radially adjacent tracks. In a second embodiment the preambles are “integrated”, meaning that the preamble is a sequence of bits that does not include separate dedicated fields, like SF and SM. The preamble bit sequences are decoded using matched filters to provide bit synchronization and start-of-data information.

Abstract: A hard disk drive has disks with data sector preambles that allow for inter-track interference. The same data sector preamble is used for all data sectors in a track but the preamble in each track is different from the preamble in radially adjacent tracks. In a first embodiment each preamble includes a synchronization field (SF) and synchronization mark (SM) that are the same in each track but different from the SF and SM in radially adjacent tracks. Only two unique SFs and two unique SMs are required, with the two SFs and two SMs alternating in radially adjacent tracks. In a second embodiment the preambles are “integrated”, meaning that the preamble is a sequence of bits that does not include separate dedicated fields, like SF and SM. The preamble bit sequences are decoded using matched filters to provide bit synchronization and start-of-data information.

Abstract: A hard disk drive has disks with data sector preambles that allow for inter-track interference. The same data sector preamble is used for all data sectors in a track but the preamble in each track is different from the preamble in radially adjacent tracks. In a first embodiment each preamble includes a synchronization field (SF) and synchronization mark (SM) that are the same in each track but different from the SF and SM in radially adjacent tracks. Only two unique SFs and two unique SMs are required, with the two SFs and two SMs alternating in radially adjacent tracks. In a second embodiment the preambles are “integrated”, meaning that the preamble is a sequence of bits that does not include separate dedicated fields, like SF and SM. The preamble bit sequences are decoded using matched filters to provide bit synchronization and start-of-data information.

Abstract: A hard disk drive has disks with data sector preambles that allow for inter-track interference. The same data sector preamble is used for all data sectors in a track but the preamble in each track is different from the preamble in radially adjacent tracks. In a first embodiment each preamble includes a synchronization field (SF) and synchronization mark (SM) that are the same in each track but different from the SF and SM in radially adjacent tracks. Only two unique SFs and two unique SMs are required, with the two SFs and two SMs alternating in radially adjacent tracks. In a second embodiment the preambles are “integrated”, meaning that the preamble is a sequence of bits that does not include separate dedicated fields, like SF and SM. The preamble bit sequences are decoded using matched filters to provide bit synchronization and start-of-data information.

Abstract: A receiver utilizes a plurality of read elements, each generating a read-back signal in response to a data track positioned beneath the read element. The plurality of read-back signals are each provided to at least one space-time interference cancellation filter, which generates a filtered output that maximizes a signal associated with one of the plurality of data tracks. The filtered output is provided to a one-dimensional Viterbi detector, which is configured to generate in response an output representative of a data sequence written to one of the plurality of data tracks.

Abstract: In a wireless communication system, a method and system for a hardware accelerator for implementing the f9 integrity algorithm in WCDMA compliant handsets are provided. Intermediate variables may be initialized in an integrity function and a first processing block of bits and at least one additional processing block of bits may be generated for the integrity function from a padded string generated from input variables. Values for a first and a second processing variable may be generated for each processing stage based on a corresponding processing block of bits and on immediately generated previous first and second processing values. The first processing value may be generated utilizing a KASUMI operation after an indication that an immediately previous generated first processing value is available. An authentication code may be generated based on a last of the second processing values and a modified integrity key.

Abstract: In a wireless communication system, a method and system for implementing an FI function in a KASUMI algorithm for accelerating cryptography in GSM/GPRS/EDGE compliant handsets are provided. An efficient implementation of the FI function may comprise a first substitution stage and a second substitution stage, where a 9-bit substitution circuit and a 7-bit substitution circuit may be used in each of the stages. A pipe register may be used to transfer and zero-extend an input to the 7-bit substitution circuit for processing with an output of the 9-bit substitution circuit. A first multiplexer and a second multiplexer may be used to select the inputs for the substitution circuits at each one of the substitution stages. A third multiplexer and a fourth multiplexer may be used to select subkeys for encryption during the first substitution stage and zero value signals during the second substitution stage.

Abstract: In a wireless communication system, a method and system for implementing an FO function in a KASUMI algorithm for accelerating cryptography in GSM/GPRS/EDGE compliant handsets are provided. An efficient implementation of the FO function may comprise circuitry provided for a pipeline state machine, an FI function, a controller, a pipe register, and an XOR operation. Signals may be generated to control each round of FI processing and to indicate when each round is complete. The pipeline state machine may provide data input and subkey to the FI function for processing. A first and a second round FI processing outputs may be transferred to the pipe register. The second round output may be clocked from the pipe register to generate a portion of the FO function output and may also be XORed with a third round output of FI processing to generate the remaining portion of the FO function output.

Abstract: In a wireless communication system, a method and system for implementing the GEA3 encryption algorithm for GPRS compliant handsets are provided. An intermediate value may be generated based on initialized input variables, a cipher key and a key modifier. A first processing block of output bits may be generated by a keystream generator from the intermediate value, the cipher key, and an indication of the processing block of output bits being processed. Additional processing blocks of output bits may also be generated by the keystream generator based on an immediately previous processing block of output bits, the intermediate value, the cipher key, and an indication of the processing block of output bits being processed. A restart signal may indicate that subsequent processing blocks of output bits may be generated by the keystream generator by utilizing the same cipher key and the generated intermediate value.

Abstract: In a wireless communication system, a method and system for hardware accelerator for implementing the f8 confidentiality algorithm in WCDMA compliant handsets are provided. Input variables may be initialized in a keystream generator and an intermediate value may be generated with a confidentiality key parameter and a key modifier. The number of processing blocks of output bits may be based on the length of the input bitstream. The processing blocks of output bits may be generated utilizing a KASUMI operation and may be based on an immediately previous processing block of output bits, the intermediate value, and an indication of the current processing block of output bits. The processing blocks of output bits may be generated after an indication that an immediately previous processing block of output bits is available. The keystream generator may indicate when a first and any additional processing blocks of output bits have been determined.

Abstract: In a wireless communication system, a method and system for implementing the A5/3 encryption algorithm for GSM and EDGE compliant handsets are provided. Input variables may be initialized in a keystream generator and an intermediate value may be generated with a cipher key parameter and a key modifier. A number of processing blocks of output bits may be determined based on a number of bits in an output keystream. The processing blocks of output bits may be generated utilizing a KASUMI operation and may be based on an immediately previous processing block of output bits, the intermediate value, and an indication of the processing block of output bits being processed. The processing blocks of output bits may be generated after an indication that an immediately previous processing block of output bits is available and may be grouped into two final blocks of output bits in the output keystream.

Abstract: In a wireless communication system, a method and system for a hardware accelerator for implementing the f9 integrity algorithm in WCDMA compliant handsets are provided. Intermediate variables may be initialized in an integrity function and a first processing block of bits and at least one additional processing block of bits may be generated for the integrity function from a padded string generated from input variables. Values for a first and a second processing variable may be generated for each processing stage based on a corresponding processing block of bits and on immediately generated previous first and second processing values. The first processing value may be generated utilizing a KASUMI operation after an indication that an immediately previous generated first processing value is available. An authentication code may be generated based on a last of the second processing values and a modified integrity key.

Abstract: In a wireless communication system, a method and system for hardware accelerator for implementing the f8 confidentiality algorithm in WCDMA compliant handsets are provided. Input variables may be initialized in a keystream generator and an intermediate value may be generated with a confidentiality key parameter and a key modifier. The number of processing blocks of output bits may be based on the length of the input bitstream. The processing blocks of output bits may be generated utilizing a KASUMI operation and may be based on an immediately previous processing block of output bits, the intermediate value, and an indication of the current processing block of output bits. The processing blocks of output bits may be generated after an indication that an immediately previous processing block of output bits is available. The keystream generator may indicate when a first and any additional processing blocks of output bits have been determined.

Abstract: In a wireless communication system, a method and system for implementing the GEA3 encryption algorithm for GPRS compliant handsets are provided. An intermediate value may be generated based on initialized input variables, a cipher key and a key modifier. A first processing block of output bits may be generated by a keystream generator from the intermediate value, the cipher key, and an indication of the processing block of output bits being processed. Additional processing blocks of output bits may also be generated by the keystream generator based on an immediately previous processing block of output bits, the intermediate value, the cipher key, and an indication of the processing block of output bits being processed. A restart signal may indicate that subsequent processing blocks of output bits may be generated by the keystream generator by utilizing the same cipher key and the generated intermediate value.

Abstract: In a wireless communication system, a method and system for implementing the A5/3 encryption algorithm for GSM and EDGE compliant handsets are provided. Input variables may be initialized in a keystream generator and an intermediate value may be generated with a cipher key parameter and a key modifier. A number of processing blocks of output bits may be determined based on a number of bits in an output keystream. The processing blocks of output bits may be generated utilizing a KASUMI operation and may be based on an immediately previous processing block of output bits, the intermediate value, and an indication of the processing block of output bits being processed. The processing blocks of output bits may be generated after an indication that an immediately previous processing block of output bits is available and may be grouped into two final blocks of output bits in the output keystream.

Abstract: In a wireless communication system, a method and system for implementing an FO function in a KASUMI algorithm for accelerating cryptography in GSM/GPRS/EDGE compliant handsets are provided. An efficient implementation of the FO function may comprise circuitry provided for a pipeline state machine, an FI function, a controller, a pipe register, and an XOR operation. Signals may be generated to control each round of FI processing and to indicate when each round is complete. The pipeline state machine may provide data input and subkey to the FI function for processing. A first and a second round FI processing outputs may be transferred to the pipe register. The second round output may be clocked from the pipe register to generate a portion of the FO function output and may also be XORed with a third round output of FI processing to generate the remaining portion of the FO function output.

Abstract: In a wireless communication system, a method and system for implementing an FI function in a KASUMI algorithm for accelerating cryptography in GSM/GPRS/EDGE compliant handsets are provided. An efficient implementation of the FI function may comprise a first substitution stage and a second substitution stage, where a 9-bit substitution circuit and a 7-bit substitution circuit may be used in each of the stages. A pipe register may be used to transfer and zero-extend an input to the 7-bit substitution circuit for processing with an output of the 9-bit substitution circuit. A first multiplexer and a second multiplexer may be used to select the inputs for the substitution circuits at each one of the substitution stages. A third multiplexer and a fourth multiplexer may be used to select subkeys for encryption during the first substitution stage and zero value signals during the second substitution stage.

Abstract: In a wireless communication system, a method and system for implementing a KASUMI algorithm for accelerating cryptography in GSM/GPRS/EDGE compliant handsets are provided. A pipelined implementation of the KASUMI algorithm may comprise a plurality of selectors, an FI function, an FO function, a first pipe register, a second pipe register, and an XOR operation. A selected first portion of the input data may be transferred to the first pipe register and a selected second portion to the second pipe register. A first output may be generated based on the transferred second portion of the input data while the transferred first portion of the input data may correspond to a second output. A plurality of control signals may control the inputs to the FO function and to the FL function according to whether the round of processing is an even round or an odd round.

Abstract: A general rate N/(N+1) (0, G), code construction, e.g., for a magnetic recording system, allows for encoding or decoding of a dataword having N elements, N preferably being an integer multiple of eight. The dataword is divided into N/8 bytes of binary data that are encoded as a run-length limited (RLL) codeword in accordance with the general rate N/(N+1) (0, G) code construction. The general rate N/(N+1) (0, G) code construction is characterized by the constraints (d=0, G=(N/4)+1, l=N/8, r=N/8). the N/(N+1) (0 (N/4)+1, N/8, N/8) RLL codeword is constructed from the dataword in accordance with 1) pivot bits identifying code violations related to the constraints, 2) correction bits set to correct code violations, and 3) preserved elements having values not included in the code violations.

Abstract: A system and method employing a rate 24/25 (0,9) code constructed in accordance with a data byte interleaved with a rate 16/17 (0,5) codeword formed from two data bytes limits the number of consecutive zeros seen by a channel to nine. The 16/17 (0,5) codeword is formed from the two data bytes in accordance with a set of pivot bits and a set of corrections for predefined code violations. The additional data byte is interleaved into the 16/17 (0,5) codeword by splitting the byte into a pair of portions and inserting the portions into the 16/17 (0,5) codeword at locations adjacent to predefined ones of the pivot bits. The rate 24/25 (0,9) code is suitable for magnetic or similar recording media and may be employed in partial response maximum likelihood read channels. A feature of the constructed code is a high transition density which allows for more frequent timing and gain control updates, which results in lower required channel input signal to noise ratio for a given channel performance.