Abstract: A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the unoccupied locations. In one embodiment, virtual ground voltage references to the logic cells are routed to their associated switch cells. Because conventional standard cell design and placement techniques achieve only a placement density or utilization between 70-80% (i.e., unoccupied space constitutes between 20 to 30% of the available space in each row of logic cells), by placing the power gate cells in the unoccupied space, the method does not increase the silicon real estate requirement even though the power gate cells are introduced into the design. Optimization techniques may be applied to achieve proper sizing and distribution of power gate cells, so as to avoid a performance penalty due to the power gate cells.

Abstract: A system and method integrates signal filters in a multiband transceiver. A preferred embodiment comprises an amplifier with a first tunable capacitor coupled to a signal input and a tunable filter. The tunable filter comprises an input stage with a first pair of inductors arranged in a dipole configuration and a second tunable capacitor coupled in parallel to the first pair of inductors and an output stage inductively coupled to the input stage, the output stage includes a second pair of inductors also arranged in a dipole configuration and a third tunable capacitor coupled in parallel to the second pair of inductors. The inductors are realized using bond wire or any other high Q material. The first tunable capacitor, the second tunable capacitor, and the third tunable capacitor can be tuned using a master-slave tuning configuration to adjust the operating frequency of the amplifier and the tunable filter to enable frequency band compatibility with multiple communications protocols.

Abstract: A system and method integrates signal filters in a multiband transceiver. A preferred embodiment comprises an amplifier with a first tunable capacitor coupled to a signal input and a tunable filter. The tunable filter comprises an input stage with a first pair of inductors arranged in a dipole configuration and a second tunable capacitor coupled in parallel to the first pair of inductors and an output stage inductively coupled to the input stage, the output stage includes a second pair of inductors also arranged in a dipole configuration and a third tunable capacitor coupled in parallel to the second pair of inductors. The inductors are realized using bond wire or any other high Q material. The first tunable capacitor, the second tunable capacitor, and the third tunable capacitor can be tuned using a master-slave tuning configuration to adjust the operating frequency of the amplifier and the tunable filter to enable frequency band compatibility with multiple communications protocols.

Abstract: A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the unoccupied locations. In one embodiment, virtual ground voltage references to the logic cells are routed to their associated switch cells. Because conventional standard cell design and placement techniques achieve only a placement density or utilization between 70-80% (i.e., unoccupied space constitutes between 20 to 30% of the available space in each row of logic cells), by placing the power gate cells in the unoccupied space, the method does not increase the silicon real estate requirement even though the power gate cells are introduced into the design. Optimization techniques may be applied to achieve proper sizing and distribution of power gate cells, so as to avoid a performance penalty due to the power gate cells.

Abstract: A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the unoccupied locations. In one embodiment, virtual ground voltage references to the logic cells are routed to their associated switch cells. Because conventional standard cell design and placement techniques achieve only a placement density or utilization between 70-80% (i.e., unoccupied space constitutes between 20 to 30% of the available space in each row of logic cells), by placing the power gate cells in the unoccupied space, the method does not increase the silicon real estate requirement even though the power gate cells are introduced into the design. Optimization techniques may be applied to achieve proper sizing and distribution of power gate cells, so as to avoid a performance penalty due to the power gate cells.

Abstract: A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the unoccupied locations. In one embodiment, virtual ground voltage references to the logic cells are routed to their associated switch cells. Because conventional standard cell design and placement techniques achieve only a placement density or utilization between 70-80% (i.e., unoccupied space constitutes between 20 to 30% of the available space in each row of logic cells), by placing the power gate cells in the unoccupied space, the method does not increase the silicon real estate requirement even though the power gate cells are introduced into the design. Optimization techniques may be applied to achieve proper sizing and distribution of power gate cells, so as to avoid a performance penalty due to the power gate cells.

Abstract: Disclosed is a semiconductor wafer with an array of integrated circuit chips with scribe lane structures forming edge and intra-chip seals for use in protecting the IC circuitry. Substantially parallel scribe seal structures extend around the periphery of each chip; the two scribe seal structures have a separation gap. Preferred embodiments of the invention also include wafers of ICs each having two or more distinctive circuitry blocks such as analog and digital circuitry, separated by an intra-chip seal. Preferred embodiments of also include ICs having two or more distinctive circuit blocks separated by a scribe seal structure with a separation gap and a routing channel for use in passing signals among the circuit blocks.

Abstract: Methods and apparatus to integrate image rejection into quadrature mixers are disclosed. A disclosed image-rejection quadrature mixer comprises a quadrature mixer, and a cross-coupled differential pair of transistors to provide a complex filter response, wherein the mixer and the transistors are integrated on a common silicon substrate.

Abstract: Methods and apparatus to bias a backgate of a power switch while preventing latchup are disclosed. A disclosed method of biasing a backgate of a power switch comprises: if a voltage of a first power supply rises before a voltage of a second power supply, initially biasing the backgate with a voltage based on the first power supply; and if the voltage of the first power supply rises after the voltage of the second power supply, biasing the backgate with a voltage based on the second power supply.

Abstract: System and method for correcting an inaccurate clock with the use of an accurate reference clock. A preferred embodiment comprises repeatedly counting clock cycles in a clock signal generated by the inaccurate clock for a specified period of time, after the completion of each specified period of time, computing a delta value based on the clock cycle counts of the clock signal of the inaccurate clock, accumulating a delta sum value, and computing a clock adjustment value for the inaccurate clock based upon the delta sum value. The reference clock is used to mark the end of each specified period of time.

Abstract: Methods and apparatus to integrate image rejection into quadrature mixers are disclosed. A disclosed image-rejection quadrature mixer comprises a quadrature mixer, and a cross-coupled differential pair of transistors to provide a complex filter response, wherein the mixer and the transistors are integrated on a common silicon substrate.

Abstract: Disclosed is a semiconductor wafer with an array of integrated circuit chips with scribe lane structures forming edge and intra-chip seals for use in protecting the IC circuitry. Substantially parallel scribe seal structures extend around the periphery of each chip; the two scribe seal structures have a separation gap. Preferred embodiments of the invention also include wafers of ICs each having two or more distinctive circuitry blocks such as analog and digital circuitry, separated by an intra-chip seal. Preferred embodiments of also include ICs having two or more distinctive circuit blocks separated by a scribe seal structure with a separation gap and a routing channel for use in passing signals among the circuit blocks.

Abstract: System and method for correcting an inaccurate clock with the use of an accurate reference clock. A preferred embodiment comprises repeatedly counting clock cycles in a clock signal generated by the inaccurate clock for a specified period of time, after the completion of each specified period of time, computing a delta value based on the clock cycle counts of the clock signal of the inaccurate clock, accumulating a delta sum value, and computing a clock adjustment value for the inaccurate clock based upon the delta sum value. The reference clock is used to mark the end of each specified period of time.

Abstract: A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the unoccupied locations. In one embodiment, virtual ground voltage references to the logic cells are routed to their associated switch cells. Because conventional standard cell design and placement techniques achieve only a placement density or utilization between 70-80% (i.e., unoccupied space constitutes between 20 to 30% of the available space in each row of logic cells), by placing the power gate cells in the unoccupied space, the method does not increase the silicon real estate requirement even though the power gate cells are introduced into the design. Optimization techniques may be applied to achieve proper sizing and distribution of power gate cells, so as to avoid a performance penalty due to the power gate cells.

Abstract: Methods and apparatus to bias a backgate of a power switch while preventing latchup are disclosed. A disclosed method of biasing a backgate of a power switch comprises: if a voltage of a first power supply rises before a voltage of a second power supply, initially biasing the backgate with a voltage based on the first power supply; and if the voltage of the first power supply rises after the voltage of the second power supply, biasing the backgate with a voltage based on the second power supply.

Abstract: A system and method integrates signal filters in a multiband transceiver. A preferred embodiment comprises an amplifier with a first tunable capacitor coupled to a signal input and a tunable filter. The tunable filter comprises an input stage with a first pair of inductors arranged in a dipole configuration and a second tunable capacitor coupled in parallel to the first pair of inductors and an output stage inductively coupled to the input stage, the output stage includes a second pair of inductors also arranged in a dipole configuration and a third tunable capacitor coupled in parallel to the second pair of inductors. The inductors are realized using bond wire or any other high Q material. The first tunable capacitor, the second tunable capacitor, and the third tunable capacitor can be tuned using a master-slave tuning configuration to adjust the operating frequency of the amplifier and the tunable filter to enable frequency band compatibility with multiple communications protocols.

Abstract: A digital tuning circuit which generates a digital code representative of a difference of signals generated by a mirror trans-conductor circuit (having electrical characteristics similar to a trans-conductor circuit in a filter) and a reference circuit. The digital code is used to adjust the trans-conductance of both the mirror trans-conductor circuit and the filter. Some of the most/more significant bits may be used to selectively activate the respective trans-conductor elements contained in the mirror trans-conductor circuit and the filter. The remaining bits may be used to fine-tune the trans-conductance of the trans-conductor elements and the filter.

Abstract: Techniques which allow a bit value stored/generated by integrated circuits to be changed by changing potentially only one of several masks used to fabricate the circuits. For example, when a single mask is to be re-designed to implement a design change (e.g., to fix minor bugs) and a version identifier is to be changed, the same mask can be used to implement the change in the version identifier as well. An embodiment allows the bit value to be changed any number of times by changing only one mask. As a result, the invention minimizes the number of masks that may need to be changed when implementing design changes.

Abstract: EMI caused on a sensitive pin by large electric current flowing through a load pin when driving a high load is reduced or substantially eliminated. An equal amount of current, but in opposite direction, is caused to be flown in another pin (“third pin”) located close to the load pin. As a result, the EMI caused by the third pin cancels the EMI generated by the load pin. During a discharge phase, a fourth pin carries and equal amount of current, but in opposite direction, to that in the load pin. The third and fourth pins may be formed by power supply pin and ground pin. A control path may avoid a path from the third pin to the fourth pin during both the charging and discharging phases. In addition, the high load may be driven by a programmable driver which uses an amount of current proportionate to the extent of load, thereby avoiding parasitic currents. EMI is further reduced as a result.

Abstract: A digital tuning circuit which generates a digital code representative of a difference of signals generated by a mirror trans-conductor circuit (having electrical characteristics similar to a trans-conductor circuit in a filter) and a reference circuit. The digital code is used to adjust the trans-conductance of both the mirror trans-conductor circuit and the filter. Some of the most/more significant bits may be used to selectively activate the respective trans-conductor elements contained in the mirror trans-conductor circuit and the filter. The remaining bits may be used to fine-tune the trans-conductance of the trans-conductor elements and the filter.