Patents by Inventor Srinivasaraman Chandrasekaran
Srinivasaraman Chandrasekaran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10320534Abstract: An integrated circuit is operable in two modes, including a test mode in which a pattern of variation is injected into a receiver's sampling clock and used to simulate jitter. Adding frequency offset, jitter or both, to this clock can be equivalent to adding jitter of an equal magnitude but opposite sign in a transmitted test signal. In this way, a clock can be produced that simulates timing variations that can be encountered during mission function operation of the device under test, while test input data is applied by local pattern generators or other data sources that, under test conditions, do not, or need not, exhibit such variations.Type: GrantFiled: January 16, 2018Date of Patent: June 11, 2019Assignee: Rambus Inc.Inventors: Srinivasaraman Chandrasekaran, Kunal Desai
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Publication number: 20180248661Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.Type: ApplicationFiled: January 16, 2018Publication date: August 30, 2018Inventors: Srinivasaraman Chandrasekaran, Kunal Desai
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Patent number: 9906335Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.Type: GrantFiled: November 25, 2016Date of Patent: February 27, 2018Assignee: Rambus Inc.Inventors: Srinivasaraman Chandrasekaran, Kunal Desai
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Publication number: 20170187498Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.Type: ApplicationFiled: November 25, 2016Publication date: June 29, 2017Inventors: Srinivasaraman Chandrasekaran, Kunal Desai
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Patent number: 9537617Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.Type: GrantFiled: February 9, 2016Date of Patent: January 3, 2017Assignee: Rambus Inc.Inventors: Srinivasaraman Chandrasekaran, Kunal Desai
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Patent number: 9444442Abstract: A Phase Interpolator (PI) may be employed as a precisely-controlled delay element in a transmit path, for example in clock forwarded serial links. Methods and circuits are disclosed for estimating a delay needed to correct duty-cycle/and or phase errors of the received clock. These corrections or delta values may be transmitted back to the transmitter side, preferably expressed directly in terms of PI phase codes, for convenient adjustment in the transmitter clock circuitry. Various techniques also are disclosed for measuring and mitigating the effects on PI integral non-linearity.Type: GrantFiled: January 27, 2014Date of Patent: September 13, 2016Assignee: RAMBUS INC.Inventors: Srinivasaraman Chandrasekaran, Gundlapalli Shanmukha Srinivas
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Publication number: 20160233991Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.Type: ApplicationFiled: February 9, 2016Publication date: August 11, 2016Inventors: Srinivasaraman Chandrasekaran, Kunal Desai
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Patent number: 9294262Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.Type: GrantFiled: May 27, 2015Date of Patent: March 22, 2016Assignee: Rambus Inc.Inventors: Srinivasaraman Chandrasekaran, Kunal Desai
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Publication number: 20150372804Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.Type: ApplicationFiled: May 27, 2015Publication date: December 24, 2015Inventors: Srinivasaraman Chandrasekaran, Kunal Desai
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Patent number: 9071407Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.Type: GrantFiled: March 18, 2013Date of Patent: June 30, 2015Assignee: Ramnus Inc.Inventors: Srinivasaraman Chandrasekaran, Kunal Desai
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Patent number: 8923442Abstract: As single-ended signaling is implemented in higher-speed communications, accurate and consistent reading of the data signal becomes increasingly challenging. In particular, single-ended links can be limited by insufficient timing margins for sampling a received input signal. A single ended receiver provides for improved timing margins by adjusting a reference voltage used to sample the input signal. A calibration pattern is provided to the receiver as the input signal, and the reference voltage is adjusted toward a median value of the signal.Type: GrantFiled: December 28, 2012Date of Patent: December 30, 2014Assignee: Rambus Inc.Inventor: Srinivasaraman Chandrasekaran
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Publication number: 20140253195Abstract: A Phase Interpolator (PI) may be employed as a precisely-controlled delay element in a transmit path, for example in clock forwarded serial links. Methods and circuits are disclosed for estimating a delay needed to correct duty-cycle/and or phase errors of the received clock. These corrections or delta values may be transmitted back to the transmitter side, preferably expressed directly in terms of PI phase codes, for convenient adjustment in the transmitter clock circuitry. Various techniques also are disclosed for measuring and mitigating the effects on PI integral non-linearity.Type: ApplicationFiled: January 27, 2014Publication date: September 11, 2014Applicant: RAMBUS INC.Inventors: Srinivasaraman Chandrasekaran, Gundlapalli Shanmukha Srinivas
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Publication number: 20130294490Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.Type: ApplicationFiled: March 18, 2013Publication date: November 7, 2013Applicant: RAMBUS INC.Inventors: Srinivasaraman Chandrasekaran, Kunal Desai