Abstract: A multi-die chip module (MCM) comprises a first die containing a first test controller and a second die containing a second test controller coupled to the first die via an interconnect. The first test controller is configured to place the first die in either a shift mode or a capture mode. The second controller is configured to place the second die in either the shift mode or the capture mode. After a scan shift operation, scan cells are initialized to predetermined values. During the capture operation one die remains in the shift mode and the other die enters the capture mode so that as test bits are shifted into registers associated with output pads on the die in the shift mode, the other die is in the capture mode and captures signals on input pads associated with that die, enabling scan based at-speed testing of the interconnect.

Abstract: A multi-die chip module (MCM) comprises a first die containing a first test controller and a second die containing a second test controller coupled to the first die via an interconnect. The first test controller is configured to place the first die in either a shift mode or a capture mode. The second controller is configured to place the second die in either the shift mode or the capture mode. After a scan shift operation, scan cells are initialized to predetermined values. During the capture operation one die remains in the shift mode and the other die enters the capture mode so that as test bits are shifted into registers associated with output pads on the die in the shift mode, the other die is in the capture mode and captures signals on input pads associated with that die, enabling scan based at-speed testing of the interconnect.

Abstract: A multi-die chip module (MCM) comprises a first die containing a first test controller and a second die containing a second test controller coupled to the first die via an interconnect. The first test controller is configured to place the first die in either a shift mode or a capture mode. The second controller is configured to place the second die in either the shift mode or the capture mode. After a scan shift operation, scan cells are initialized to predetermined values. During the capture operation one die remains in the shift mode and the other die enters the capture mode so that as test bits are shifted into registers associated with output pads on the die in the shift mode, the other die is in the capture mode and captures signals on input pads associated with that die, enabling scan based at-speed testing of the interconnect.

Abstract: A built-in self-test (BIST) diagnostic system tests the execution of a processor. The processor is arranged to execute a normal application for controlling a process that is external to the processor. The normal execution is executed in normal execution timeslots that have idle timeslots that are interspersed in time between the normal execution timeslots. A BIST controller is arranged to detect the presence of an idle timeslot in the execution of the processor and to use a scan chain to scan-in a first test pattern for a test application for testing the processor. The first test pattern is executed by the processor during the detected idle timeslot and a first result pattern generated by the execution of the first test pattern is scanned-out. The scanned-out first test pattern is evaluated to determine the presence of an error. The first test pattern application is conditionally interruptible.

Abstract: This invention generates the random seed patterns using simple, low-area overhead digital circuitry on-chip. This circuit is implemented as a finite state machine whose states are the seeds as contrasted to storing the seeds in the prior art. These seeds are used to control pseudo-random pattern generation for built-in self-tests. This invention provides a large reduction in chip area in comparison with storing seeds on-chip or off-chip.

Abstract: A built-in self-test (BIST) diagnostic system tests the execution of a processor. The processor is arranged to execute a normal application for controlling a process that is external to the processor. The normal execution is executed in normal execution timeslots that have idle timeslots that are interspersed in time between the normal execution timeslots. A BIST controller is arranged to detect the presence of an idle timeslot in the execution of the processor and to use a scan chain to scan-in a first test pattern for a test application for testing the processor. The first test pattern is executed by the processor during the detected idle timeslot and a first result pattern generated by the execution of the first test pattern is scanned-out. The scanned-out first test pattern is evaluated to determine the presence of an error. The first test pattern application is conditionally interruptible.

Abstract: A multi-die chip module (MCM) comprises a first die containing a first test controller and a second die containing a second test controller coupled to the first die via an interconnect. The first test controller is configured to place the first die in either a shift mode or a capture mode. The second controller is configured to place the second die in either the shift mode or the capture mode. After a scan shift operation, scan cells are initialized to predetermined values. During the capture operation one die remains in the shift mode and the other die enters the capture mode so that as test bits are shifted into registers associated with output pads on the die in the shift mode, the other die is in the capture mode and captures signals on input pads associated with that die, enabling scan based at-speed testing of the interconnect.

Abstract: This invention generates the random seed patterns using simple, low-area overhead digital circuitry on-chip. This circuit is implemented as a finite state machine whose states are the seeds as contrasted to storing the seeds in the prior art. These seeds are used to control pseudo-random pattern generation for built-in self-tests. This invention provides a large reduction in chip area in comparison with storing seeds on-chip or off-chip.