Patents by Inventor Srinjoy Das

Srinjoy Das has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8848731
    Abstract: System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: September 30, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Srinjoy Das, Philip Crary, Alexander Raykhman
  • Patent number: 8566491
    Abstract: System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: October 22, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Srinjoy Das, Philip Crary, Alexander Raykhman
  • Patent number: 8433944
    Abstract: In a particular embodiment, a single step increment calculation module is responsive to a first ramp control value and a second ramp control value. The single step increment calculation module generates a single step frequency adjustment as an output. The generated single step frequency adjustment is applied to a system clock signal having a first frequency to change the system clock signal to a second clock signal having a second frequency. The first frequency is different from the second frequency and the system clock signal has a first duty cycle that is within a tolerance range of a second duty cycle of the second clock signal.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: April 30, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Srinjoy Das, Haikun Zhu, Kevin R. Bowles, Matthew L. Severson
  • Publication number: 20120198117
    Abstract: System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.
    Type: Application
    Filed: July 19, 2011
    Publication date: August 2, 2012
    Inventors: Srinjoy Das, Philip Crary, Alexander Raykhman
  • Publication number: 20120198181
    Abstract: System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.
    Type: Application
    Filed: July 19, 2011
    Publication date: August 2, 2012
    Inventors: Srinjoy Das, Philip Crary, Alexander Raykhman
  • Publication number: 20120195350
    Abstract: System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.
    Type: Application
    Filed: July 19, 2011
    Publication date: August 2, 2012
    Inventors: Srinjoy Das, Philip Crary, Alexander Raykhman
  • Publication number: 20120198267
    Abstract: System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.
    Type: Application
    Filed: July 19, 2011
    Publication date: August 2, 2012
    Inventors: Srinjoy Das, Philip Crary, Alexander Raykhman
  • Publication number: 20110248764
    Abstract: In a particular embodiment, a single step increment calculation module is responsive to a first ramp control value and a second ramp control value. The single step increment calculation module generates a single step frequency adjustment as an output. The generated single step frequency adjustment is applied to a system clock signal having a first frequency to change the system clock signal to a second clock signal having a second frequency. The first frequency is different from the second frequency and the system clock signal has a first duty cycle that is within a tolerance range of a second duty cycle of the second clock signal.
    Type: Application
    Filed: April 12, 2010
    Publication date: October 13, 2011
    Applicant: QUALCOMM INCORPORATED
    Inventors: Srinjoy Das, Haikun Zhu, Kevin R. Bowles, Matthew L. Severson
  • Patent number: 6421757
    Abstract: A method and apparatus for automating and controlling the programming operations in a flash memory is provided to enable a microcontroller to accomplish various other controlling tasks while the programming operations are being conducted. A state machine is provided for controlling a plurality of sequences utilized in programming the flash memory, with various functional circuits provided to facilitate the programming and verification of flash memory cells. In a preferred embodiment, the reprogramming of the flash cells is limited to those flash cells verified as a programming failure, thus reducing the necessary programming of the flash memory cells which may impede the ability to program those flash cells. The control system may also be configured to provide for automating and controlling the erasing operations in a flash memory. The common interface circuitry may be employed to facilitates automation and control of both programming and erasing functions.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: July 16, 2002
    Assignee: Conexant Systems, Inc
    Inventors: Peiqing Wang, Srinjoy Das
  • Patent number: 6233178
    Abstract: Pre-conditioning method and apparatus for mitigating erase-induced stress within flash memory devices are disclosed. The pre-condition method includes subjecting flash memory cell to a short write process to at least partially discharge the cells. The pre-condition process is applied to an entire sector at one time, and is performed immediately prior to erasing (charging) the cells within the sector.
    Type: Grant
    Filed: October 14, 1999
    Date of Patent: May 15, 2001
    Assignee: Conexant Systems, Inc.
    Inventors: Shyam Krishnamurthy, Srinjoy Das, Michael Le, Frank Van Gieson, Surya Bhattacharya, Umesh Sharma