Patents by Inventor Sripad Nagarad

Sripad Nagarad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Tunable spacers for improved gapfill
    Patent number: 8236678
    Abstract: A device that includes a substrate with an active region is disclosed. The device includes a gate disposed in the active region and tunable sidewall spacers on sidewalls of the gate. A profile of the tunable sidewall spacers includes upper and lower portions in which width of the spacers in the upper portion is reduced at a greater rate than the lower portion.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: August 7, 2012
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Ramachandramurthy Pradeep Yelehanka, Shailendra Mishra, Sripad Nagarad
  • TUNABLE SPACERS FOR IMPROVED GAPFILL
    Publication number: 20100148269
    Abstract: A device that includes a substrate with an active region is disclosed. The device includes a gate disposed in the active region and tunable sidewall spacers on sidewalls of the gate. A profile of the tunable sidewall spacers includes upper and lower portions in which width of the spacers in the upper portion is reduced at a greater rate than the lower portion.
    Type: Application
    Filed: December 17, 2008
    Publication date: June 17, 2010
    Applicant: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Ramachandramurthy Pradeep YELEHANKA, Shailendra MISHRA, Sripad NAGARAD
  • Process integration scheme of SONOS technology
    Patent number: 7585746
    Abstract: In an non-limiting example, we provide a substrate having a cell region, and non-cell regions. We form a tunneling dielectric layer, a charge storing layer, a top insulating layer (e.g., ONO), over the substrate. Then we form a conductive pad layer over the top insulating layer. We form isolation trenches in the pad layer, the charge storing layer and the tunneling dielectric layer and into the substrate. We form isolation regions in the isolation trenches. We remove the pad layer, charge storing layer and the tunneling dielectric layer in the non-cell regions. We form a gate layer over the pad layer and the substrate surface. We complete to form the memory (e.g., SONOS) device in the cell region and other devices in the non-cell regions of the substrate.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: September 8, 2009
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Sung Mun Jung, Yoke Leng Louis Lim, Sripad Nagarad, Dong Kyun Sohn, Dong Hua Liu, Xiao Yu Chen, Rachel Low
  • Process integration scheme of SONOS technology
    Publication number: 20080014707
    Abstract: In an non-limiting example, we provide a substrate having a cell region, and non-cell regions. We form a tunneling dielectric layer, a charge storing layer, a top insulating layer (e.g., ONO), over the substrate. Then we form a conductive pad layer over the top insulating layer. We form isolation trenches in the pad layer, the charge storing layer and the tunneling dielectric layer and into the substrate. We form isolation regions in the isolation trenches. We remove the pad layer, charge storing layer and the tunneling dielectric layer in the non-cell regions. We form a gate layer over the pad layer and the substrate surface. We complete to form the memory (e.g., SONOS) device in the cell region and other devices in the non-cell regions of the substrate.
    Type: Application
    Filed: July 12, 2006
    Publication date: January 17, 2008
    Inventors: Sung Mun Jung, Yoke Leng Louis Lim, Sripad Nagarad, Dong Kyun Sohn, Dong Hua Liu, Xiao Yu Chen, Rachel Low