Patents by Inventor Sriraj Chellappan

Sriraj Chellappan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CLOCK SHAPER CIRCUIT FOR TRANSITION FAULT TESTING
    Publication number: 20230243887
    Abstract: An integrated circuit for transition fault testing comprises a synchronizing circuit including a first set of shift registers coupled to receive a scan enable signal and to provide a synchronizing signal based on the scan enable signal; a clock leaker circuit coupled to the synchronizing circuit and including a second set of shift registers coupled to receive a first clock signal based on the synchronizing signal and to provide a second clock signal that includes a set of pulses; and a multiplexer (MUX) that includes a first input coupled to receive a shift clock, a second input coupled to the clock leaker circuit to receive the second clock signal, and an output configured to provide an output clock signal that includes a second set of pulses.
    Type: Application
    Filed: March 13, 2023
    Publication date: August 3, 2023
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Wilson Pradeep, Sriraj Chellappan, Shruti Gupta
  • Clock shaper circuit for transition fault testing
    Patent number: 11604221
    Abstract: An integrated circuit for transition fault testing comprises a synchronizing circuit including a first set of shift registers coupled to receive a scan enable signal and to provide a synchronizing signal based on the scan enable signal; a clock leaker circuit coupled to the synchronizing circuit and including a second set of shift registers coupled to receive a first clock signal based on the synchronizing signal and to provide a second clock signal that includes a set of pulses; and a multiplexer (MUX) that includes a first input coupled to receive a shift clock, a second input coupled to the clock leaker circuit to receive the second clock signal, and an output configured to provide an output clock signal that includes a second set of pulses.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: March 14, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Wilson Pradeep, Sriraj Chellappan, Shruti Gupta