Patents by Inventor Sriraj Manavalan

Sriraj Manavalan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices
    Patent number: 9401363
    Abstract: A vertical transistor device includes a line of active area adjacent a line of dielectric isolation. A buried data/sense line obliquely angles relative to the line of active area and the line of dielectric isolation. A pair of gate lines is outward of the buried data/sense line and obliquely angle relative to the line of active area and the line of dielectric isolation. A vertical transistor channel region is within the active area between the pair of gate lines. An outer source/drain region is in the active area above the channel region and an inner source/drain region is in the active area below the channel region. The inner source/drain region is electrically coupled to the buried data/sense line. Other devices and structures are contemplated, as are methods of forming a plurality of vertical transistor devices.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: July 26, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Kuo Chen Wang, Sriraj Manavalan, Wei Ming Liao
  • Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices
    Patent number: 9287271
    Abstract: A vertical transistor device includes a line of active area adjacent a line of dielectric isolation. A buried data/sense line obliquely angles relative to the line of active area and the line of dielectric isolation. A pair of gate lines is outward of the buried data/sense line and obliquely angle relative to the line of active area and the line of dielectric isolation. A vertical transistor channel region is within the active area between the pair of gate lines. An outer source/drain region is in the active area above the channel region and an inner source/drain region is in the active area below the channel region. The inner source/drain region is electrically coupled to the buried data/sense line. Other devices and structures are contemplated, as are methods of forming a plurality of vertical transistor devices.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: March 15, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Kuo Chen Wang, Sriraj Manavalan, Wei Ming Liao
  • Vertical Transistor Devices, Memory Arrays, And Methods Of Forming Vertical Transistor Devices
    Publication number: 20150236023
    Abstract: A vertical transistor device includes a line of active area adjacent a line of dielectric isolation. A buried data/sense line obliquely angles relative to the line of active area and the line of dielectric isolation. A pair of gate lines is outward of the buried data/sense line and obliquely angle relative to the line of active area and the line of dielectric isolation. A vertical transistor channel region is within the active area between the pair of gate lines. An outer source/drain region is in the active area above the channel region and an inner source/drain region is in the active area below the channel region. The inner source/drain region is electrically coupled to the buried data/sense line. Other devices and structures are contemplated, as are methods of forming a plurality of vertical transistor devices.
    Type: Application
    Filed: April 29, 2015
    Publication date: August 20, 2015
    Inventors: Kuo Chen Wang, Sriraj Manavalan, Wei Ming Liao
  • Vertical Transistor Devices, Memory Arrays, And Methods Of Forming Vertical Transistor Devices
    Publication number: 20130049110
    Abstract: A vertical transistor device includes a line of active area adjacent a line of dielectric isolation. A buried data/sense line obliquely angles relative to the line of active area and the line of dielectric isolation. A pair of gate lines is outward of the buried data/sense line and obliquely angle relative to the line of active area and the line of dielectric isolation. A vertical transistor channel region is within the active area between the pair of gate lines. An outer source/drain region is in the active area above the channel region and an inner source/drain region is in the active area below the channel region. The inner source/drain region is electrically coupled to the buried data/sense line. Other devices and structures are contemplated, as are methods of forming a plurality of vertical transistor devices.
    Type: Application
    Filed: August 23, 2011
    Publication date: February 28, 2013
    Inventors: Kuo Chen Wang, Sriraj Manavalan, Wei Ming Liao