Abstract: Worst case performance of an SRAM cell may be simulated more accurately with less intensive computations. An embodiment includes determining, by a processor, a process corner G of an SRAM cell, having pull-down, pass-gate, and pull-up devices, process corner G being defined as the worst performance of the cell when only global variations of parameters of the SRAM cell are included, setting each of the pull-down, pass-gate, and pull-up devices at process corner G, performing, on the processor, a number of Monte Carlo simulations of the SRAM cell devices around process corner G with only local variations of the parameters, generating a normal probability distribution for Iread based on the local Monte Carlo simulations around process corner G, extrapolating the worst case Iread from the normal probability distribution of Iread to define a process corner SRM representing a slowest SRAM bit on a chip, and validating an SRAM cell based on the SRM corner.

Abstract: Described herein are compounds and pharmaceutical compositions containing such compounds, which inhibit the activity of histone deacetylase 8 (HDAC8). Also described herein are methods of using such HDAC8 inhibitors, alone and in combination with other compounds, for treating diseases or conditions that would benefit from inhibition of HDAC8 activity.

Abstract: A semiconductor device is provided that includes a first pair of P channel field effect transistors (PFET) with a common source connected to a voltage contact and a gate connected to a drain of the other PFET and a pair of N channel field effect transistors (NFET) sized smaller than the first pair of PFETs with a drain connected to the drain of the respective PFET of the first pair of PFETs, a common source connected to a ground contact, and a gate connected to the drain of an opposite PFET of the first pair of PFETs. Additionally, a second pair of PFETs sized larger than the NFETs and approximately one-half that of the first pair of PFETS, each of the second pair of PFETs having a drain respectively coupled to a connection linking the respective drain of the NFET of the pair of NFETs to the drain of the PFET of the first pair of PFETs. Complementary bit lines are included, each of the complementary bit lines respectively connected to a source of the second pair of PFETs.

Abstract: MOS structures that exhibit lower contact resistance and methods for fabricating such MOS structures are provided. In one method, a semiconductor substrate is provided and a gate stack is fabricated on the semiconductor substrate. With the gate stack serving as a mask, impurity dopants are implanted into a semiconductor material having a first surface and disposed proximate to the gate stack. A trench is etched into the semiconductor material such that the semiconductor material has a trench surface within the trench. Further, a metal silicide layer is formed on the first surface of the semiconductor material and on the trench surface. Also, a contact to at least a portion of the metal silicide layer on the first surface and at least a portion of the metal silicide layer on the trench surface is fabricated.

Abstract: Worst case performance of an SRAM cell may be simulated more accurately with less intensive computations. An embodiment includes determining, by a processor, a process corner G of an SRAM cell, having pull-down, pass-gate, and pull-up devices, process corner G being defined as the worst performance of the cell when only global variations of parameters of the SRAM cell are included, setting each of the pull-down, pass-gate, and pull-up devices at process corner G, performing, on the processor, a number of Monte Carlo simulations of the SRAM cell devices around process corner G with only local variations of the parameters, generating a normal probability distribution for Iread based on the local Monte Carlo simulations around process corner G, extrapolating the worst case Iread from the normal probability distribution of Iread to define a process corner SRM representing a slowest SRAM bit on a chip, and validating an SRAM cell based on the SRM corner.

Abstract: Dosing regimens, methods of treatment, controlled release formulations, and combination therapies that include an HDAC inhibitor, or a pharmaceutically acceptable salt thereof, are described.

Abstract: MOS structures that exhibit lower contact resistance and methods for fabricating such MOS structures are provided. In one method, a semiconductor substrate is provided and a gate stack is fabricated on the semiconductor substrate. With the gate stack serving as a mask, impurity dopants are implanted into a semiconductor material having a first surface and disposed proximate to the gate stack. A trench is etched into the semiconductor material such that the semiconductor material has a trench surface within the trench. Further, a metal silicide layer is formed on the first surface of the semiconductor material and on the trench surface. Also, a contact to at least a portion of the metal silicide layer on the first surface and at least a portion of the metal silicide layer on the trench surface is fabricated.

Abstract: MOS structures that exhibit lower contact resistance and methods for fabricating such MOS structures are provided. In one method, a semiconductor substrate is provided and a gate stack is fabricated on the semiconductor substrate. An impurity-doped region within the semiconductor substrate aligned with the gate stack is formed. Adjacent contact fins extending from the impurity-doped region are fabricated and a metal silicide layer is formed on the contact fins. A contact to at least a portion of the metal silicide layer on at least one of the contact fins is fabricated.

Abstract: Described herein are methods for treating a subject suffering from an inflammatory, autoimmune, or heteroimmune condition by administering to the subject a pharmaceutical composition containing a therapeutically effective amount of a compound that is a selective inhibitor of histone deacetylase 8. Also described herein are methods for decreasing secretion of pro-inflammatory cytokines by administering an HDAC8-selective inhibitor compound. Further described herein are methods for predicting responsiveness to treatments for inflammatory conditions. Methods for predicting efficacy of treatments for inflammatory conditions are also described.

Abstract: Described herein are compounds and pharmaceutical compositions containing such compounds, which inhibit the activity of histone deacetylase 8 (HDAC8). Also described herein are methods of using such HDAC8 inhibitors, alone and in combination with other compounds, for treating diseases or conditions that would benefit from inhibition of HDAC8 activity.

Abstract: Described herein are methods and compositions for determining whether a particular cancer is resistant to or susceptible to a histone deacetylase inhibitor or to histone deacetylase inhibitors. The methods include analysis of the expression levels of at least four biomarker genes associated with response to a histone deacetylase inhibitor. Also described herein are methods and compositions for increasing the likelihood of a therapeutically effective treatment in a patient, comprising an analysis of the expression levels of at least four biomarker genes associated with response to a histone deacetylase inhibitor. Also described herein are isolated populations of nucleic acids derived from a cancer sensitive to or resistant to a histone deacetylase inhibitor. Further described are kits and indications that are optionally used in conjunction with the aforementioned methods and compositions.

Abstract: Described herein are methods and compositions for determining whether a particular cancer is resistant to or susceptible to a histone deacetylase inhibitor or to histone deacetylase inhibitors. The methods include analysis of the expression levels of at least four biomarker genes associated with response to a histone deacetylase inhibitor. Also described herein are methods and compositions for increasing the likelihood of a therapeutically effective treatment in a patient, comprising an analysis of the expression levels of at least four biomarker genes associated with response to a histone deacetylase inhibitor. Also described herein are isolated populations of nucleic acids derived from a cancer sensitive to or resistant to a histone deacetylase inhibitor. Further described are kits and indications that are optionally used in conjunction with the aforementioned methods and compositions.

Abstract: Described herein are methods for using calcium flux as a biomarker to select and predict patients likely to respond to an apoptotic agent as therapy. Further described herein is a method of using calcium flux as a clinical biomarker to determine whether a tumor is sensitive to an HDAC inhibitor.

Abstract: Described herein are methods for treating a subject suffering from a T-cell lymphoma by administering to the subject a pharmaceutical composition containing a therapeutically effective amount of a selective inhibitor of histone deacetylase 8. Also described herein are methods for treating a subject suffering from a T-cell lymphoma by administering to the subject a population of autologous T-cells that have been exposed to a selective HDAC8 inhibitor composition ex vivo.

Abstract: A method of modeling an SRAM cell is provided. Initially, transistor models are provided based on transistor devices, and an SRAM cell model is provided including the transistor models. The present methodology streamlines the modeling process by modeling in order the pull up, pass gate and pull down transistors so as to minimize the number of transistor modeling iterations needed, and by focusing on the specific areas of transistor operation to achieve the desired level of operational accuracy. Variations to the model are provided, mimicking variations in data from actual devices, and yield based on failure estimation is measured using the model and its variations.

Abstract: Described herein are methods and compositions for determining whether a particular cancer is resistant to or susceptible to a histone deacetylase inhibitor or to histone deacetylase inhibitors. The methods include analysis of the expression levels of at least four biomarker genes associated with response to a histone deacetylase inhibitor. Also described herein are methods and compositions for increasing the likelihood of a therapeutically effective treatment in a patient, comprising an analysis of the expression levels of at least four biomarker genes associated with response to a histone deacetylase inhibitor. Also described herein are isolated populations of nucleic acids derived from a cancer sensitive to or resistant to a histone deacetylase inhibitor. Further described are kits and indications that are optionally used in conjunction with the aforementioned methods and compositions.

Abstract: MOS structures that exhibit lower contact resistance and methods for fabricating such MOS structures are provided. In one method, a semiconductor substrate is provided and a gate stack is fabricated on the semiconductor substrate. An impurity-doped region within the semiconductor substrate aligned with the gate stack is formed. Adjacent contact fins extending from the impurity-doped region are fabricated and a metal silicide layer is formed on the contact fins. A contact to at least a portion of the metal silicide layer on at least one of the contact fins is fabricated.

Abstract: Embodiments of the present invention can provide circuits and systems for computing a discrete Fourier transform (DFT) or an inverse discrete Fourier transform (IDFT). An embodiment includes an input circuit, an intermediate circuit, an output circuit, and an accumulator circuit. The input circuit can receive a set of input values, and can use a first set of degenerate rotators to generate a first set of intermediate values. The intermediate circuit can receive the first set of intermediate values, and can use a set of CORDICs (coordinate rotation digital computers) to generate a second set of intermediate values. The output circuit can receive the second set of intermediate values, and can use a second set of degenerate rotators to generate a third set of intermediate values. The accumulator circuit can receive the third set of intermediate values, and can use a set of accumulators to generate a set of output values.

Abstract: An XLANG/s compiler detects convoy scenarios during compilation and generates runtime directives to correctly correlate incoming messages with business process instances. A convoy scenario, present in event driven processes, is defined by a correlation set initialized during a receive operation which is provided to a subsequent receive operation. The compiler detects those convoy scenarios by analyzing the control and dataflow of a XLANG/s program. Three convoy patterns are distinguished: (1) activation convoys, (2) uniform sequential convoys, and (3) non-uniform sequential convoys. XLANG/s allows declarative descriptions of convoy scenarios without requiring an understanding of the low-level details supporting their correct execution. Convoy scenarios are processed by statically analyzing a written workflow application to deduce the nature and type of convoy scenarios used by the application. Information is extracted at compile time to support the runtime infrastructure.

Abstract: Described herein are methods for treating a subject suffering from a T-cell lymphoma by administering to the subject a pharmaceutical composition containing a therapeutically effective amount of a selective inhibitor of histone deacetylase 8. Also described herein are methods for treating a subject suffering from a T-cell lymphoma by administering to the subject a population of autologous T-cells that have been exposed to a selective HDAC8 inhibitor composition ex vivo.