Patents by Inventor Sriram Chandrasekaran

Sriram Chandrasekaran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250118706
    Abstract: A chip package and method for fabricating the same are provided that include a IC dies bonded to a thermal carrier having a plurality of metallic pillars. In one example, a chip package includes an interconnect routing structure and a first die disposed on a first surface of the interconnect routing structure. The first die has a circuitry connected to a circuitry of the interconnect routing structure. The chip package also includes a second die at least partially disposed over the first die. The second die has a circuitry connected to the circuitry of the first die. A thermal carrier is bonded on the second die. At least one of the thermal carrier, the first die, or the second die includes a plurality of metallic pillars configured to transfer heat, wherein the plurality of metallic pillars are electrically floating.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 10, 2025
    Inventors: Manish DUBEY, Arsalan ALAM, Hemanth Kumar DHAVALESWARAPU, Chandra Sekhar MANDALAPU, Sriram CHANDRASEKARAN
  • Publication number: 20250112113
    Abstract: A method can include embedding one or more thermal sources in a semiconductor package substrate and positioning one or more substrate buildup layers above the one or more thermal sources. The method can also include forming one or more thermal vias in the one or more substrate buildup layers. Various other methods and systems are also disclosed.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Sriram Chandrasekaran, Hemanth Kumar Dhavaleswarapu, Robert Grant Spurney
  • Publication number: 20240418750
    Abstract: A system having: a power switching circuit providing a drive current to a load, and having: a power source; first and second serially connected switches convert DC power from the power source into AC current to form the drive current, or vice versa; a first high-bandwidth current sensor circuit measures high-side current pulses through the first switch and provides a first analog signal, proportional to the high-side pulses; a second high-bandwidth current sensor circuit measures low-side current pulses through the second switch and provides a second analog signal is proportional to the low-side pulses; a signal processing device coupled to the first and second current sensor circuits performs steps of: converting the first analog signal to a first digital signal and the second analog signal to a second digital signal; and reconstructing the drive current and obtaining its cycle average values from the first and second digital signals.
    Type: Application
    Filed: June 16, 2023
    Publication date: December 19, 2024
    Inventors: Suman Dwari, Weilun Chen, Yongduk Lee, Sriram Chandrasekaran
  • Publication number: 20240355528
    Abstract: An example integrated transformer is provided having a core. A first set of windings encircles a first region around the core. A second set of windings encircles a second region around the core, wherein the first region and the second region are not the same. At least one insert separates magnetic flux induced by the first set of windings and the second set of windings enabling increased magnetic inductance with reduced winding losses.
    Type: Application
    Filed: April 18, 2023
    Publication date: October 24, 2024
    Applicant: Raytheon Company
    Inventors: Jeffrey Ewanchuk, Weilun Chen, Suman Dwari, Sriram Chandrasekaran
  • Patent number: 11979084
    Abstract: An isolated DC/DC converter includes a primary stage, a transformer circuit, a secondary stage, an active clamp, a first current sense node, and a second current sense node. The primary stage includes a primary switching inverter configured to invert the source DC voltage into a high-frequency alternating current (AC) voltage. The transformer circuit adjusts an AC voltage level of the high-frequency AC voltage and outputs an adjusted AC voltage. The secondary stage includes a secondary switching converter to convert the adjusted AC voltage into a secondary voltage, and the active clamp is configured to clamp the secondary voltage to provide an output DC voltage. The first current sense node is included in the primary stage conducts a source current having a first current level, and the second current sense node is included in the secondary stage and conducts a clamp current having a second current level.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: May 7, 2024
    Assignee: RAYTHEON COMPANY
    Inventors: Sriram Chandrasekaran, Bruce Stoltz, Marty Perry, Noel Delgado
  • Publication number: 20240079149
    Abstract: Systems, methods, and computer-readable medium storing instructions of using transfer machine learning for predicting drug interaction outcomes include: obtaining a trained machine learning model, obtaining genetic information of pathogens of interest, generating predicted drug interaction outcome data for drug treatments of interest using the machine learning model, and indicating the predicted drug interaction outcome data. The machine learning model may be trained by obtaining training data, classifying the training data into subsets corresponding to different actual outcomes, and generating the machine learning model using the classified subsets. The training data may include drug interaction outcome data having, for each respective pathogen of the pathogens, an outcome of drug treatments applied to the respective pathogen.
    Type: Application
    Filed: April 26, 2023
    Publication date: March 7, 2024
    Inventor: Sriram Chandrasekaran
  • Publication number: 20240072641
    Abstract: An isolated DC/DC converter includes a primary stage, a transformer circuit, a secondary stage, an active clamp, a first current sense node, and a second current sense node. The primary stage includes a primary switching inverter configured to invert the source DC voltage into a high-frequency alternating current (AC) voltage. The transformer circuit adjusts an AC voltage level of the high-frequency AC voltage and outputs an adjusted AC voltage. The secondary stage includes a secondary switching converter to convert the adjusted AC voltage into a secondary voltage, and the active clamp is configured to clamp the secondary voltage to provide an output DC voltage. The first current sense node is included in the primary stage conducts a source current having a first current level, and the second current sense node is included in the secondary stage and conducts a clamp current having a second current level.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Sriram Chandrasekaran, Bruce Stoltz, Marty Perry, Noel Delgado
  • Patent number: 11847629
    Abstract: Disclosed are various embodiments for resilient workflows dependent on external computing systems. In one embodiment, one or more steps in a workflow are determined to invoke a request to an external computing system. Availability information for the external computing system is determined. The external computing system is detected to be potentially unavailable before a request within a workflow is submitted via an application programming interface (API) for processing by the external computing system. An indication is provided that an integration with the external computing system is unavailable in response to detecting that the external computing system is potentially unavailable.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: December 19, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Uttaresh Mehta, Lakhshya Bansal, Sriram Chandrasekaran, Karthik Seetharaman
  • Patent number: 10784859
    Abstract: A gate drive circuit for generating asymmetric drive voltages comprises a gate drive transformer comprising: a primary winding responsive to a pulse width module (PWM) input signal to generate a bipolar signal having a positive bias voltage and a negative bias voltage; and a secondary winding responsive to the bipolar signal to generate a PWM output signal. A first charge pump is connected to the secondary winding responsive to the PWM output signal to generate a level shifted PWM output signal. A second charge pump is connected to the secondary winding to generate a readjusted PWM output signal by decreasing at least a portion of the level shifted PWM output signal. A gate switching device is connected to the first charge pump and second charge pump. A level shifted PWM output signal establishes an ON condition and the readjusted PWM output signal establishes an OFF condition of the gate MOSFET.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: September 22, 2020
    Assignee: Raytheon Company
    Inventors: Sriram Chandrasekaran, Michael S. Hockema
  • Patent number: 10778218
    Abstract: A gate drive circuit for generating asymmetric drive voltages comprises a gate drive transformer comprising: a primary winding responsive to a pulse width module (PWM) input signal to generate a bipolar signal having a positive bias voltage and a negative bias voltage; and a secondary winding responsive to the bipolar signal to generate a PWM output signal. A first charge pump is connected to the secondary winding responsive to the PWM output signal to generate a level shifted PWM output signal. A second charge pump is connected to the secondary winding to generate a readjusted PWM output signal by decreasing at least a portion of the level shifted PWM output signal. A gate switching device is connected to the first charge pump and second charge pump. A level shifted PWM output signal establishes an ON condition and the readjusted PWM output signal establishes an OFF condition of the gate MOSFET.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: September 15, 2020
    Assignee: Raytheon Company
    Inventors: Sriram Chandrasekaran, Michael S. Hockema
  • Publication number: 20200106436
    Abstract: A gate drive circuit for generating asymmetric drive voltages comprises a gate drive transformer comprising: a primary winding responsive to a pulse width module (PWM) input signal to generate a bipolar signal having a positive bias voltage and a negative bias voltage; and a secondary winding responsive to the bipolar signal to generate a PWM output signal. A first charge pump is connected to the secondary winding responsive to the PWM output signal to generate a level shifted PWM output signal. A second charge pump is connected to the secondary winding to generate a readjusted PWM output signal by decreasing at least a portion of the level shifted PWM output signal. A gate switching device is connected to the first charge pump and second charge pump. A level shifted PWM output signal establishes an ON condition and the readjusted PWM output signal establishes an OFF condition of the gate MOSFET.
    Type: Application
    Filed: July 23, 2019
    Publication date: April 2, 2020
    Inventors: Sriram Chandrasekaran, Michael S. Hockema
  • Publication number: 20200106435
    Abstract: A gate drive circuit for generating asymmetric drive voltages comprises a gate drive transformer comprising: a primary winding responsive to a pulse width module (PWM) input signal to generate a bipolar signal having a positive bias voltage and a negative bias voltage; and a secondary winding responsive to the bipolar signal to generate a PWM output signal. A first charge pump is connected to the secondary winding responsive to the PWM output signal to generate a level shifted PWM output signal. A second charge pump is connected to the secondary winding to generate a readjusted PWM output signal by decreasing at least a portion of the level shifted PWM output signal. A gate switching device is connected to the first charge pump and second charge pump. A level shifted PWM output signal establishes an ON condition and the readjusted PWM output signal establishes an OFF condition of the gate MOSFET.
    Type: Application
    Filed: July 23, 2019
    Publication date: April 2, 2020
    Inventors: Sriram Chandrasekaran, Michael S. Hockema
  • Patent number: 10574129
    Abstract: A reconfigurable power converter is provided that includes a pulse-width modulation (PWM) controller. The PWM controller is configured to switch between a first modulation scheme and a second modulation scheme when a current-level property crosses a transition threshold.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: February 25, 2020
    Assignee: Raytheon Company
    Inventor: Sriram Chandrasekaran
  • Publication number: 20190341840
    Abstract: A reconfigurable power converter is provided that includes a pulse-width modulation (PWM) controller. The PWM controller is configured to switch between a first modulation scheme and a second modulation scheme when a current-level property crosses a transition threshold.
    Type: Application
    Filed: May 4, 2018
    Publication date: November 7, 2019
    Inventor: Sriram Chandrasekaran
  • Patent number: 10361698
    Abstract: A gate drive circuit for generating asymmetric drive voltages comprises a gate drive transformer comprising: a primary winding responsive to a pulse width module (PWM) input signal to generate a bipolar signal having a positive bias voltage and a negative bias voltage; and a secondary winding responsive to the bipolar signal to generate a PWM output signal. A first charge pump is connected to the secondary winding responsive to the PWM output signal to generate a level shifted PWM output signal. A second charge pump is connected to the secondary winding to generate a readjusted PWM output signal by decreasing at least a portion of the level shifted PWM output signal. A gate switching device is connected to the first charge pump and second charge pump. A level shifted PWM output signal establishes an ON condition and the readjusted PWM output signal establishes an OFF condition of the gate MOSFET.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: July 23, 2019
    Assignee: Raytheon Company
    Inventors: Sriram Chandrasekaran, Michael S. Hockema
  • Publication number: 20180241391
    Abstract: A gate drive circuit for generating asymmetric drive voltages comprises a gate drive transformer comprising: a primary winding responsive to a pulse width module (PWM) input signal to generate a bipolar signal having a positive bias voltage and a negative bias voltage; and a secondary winding responsive to the bipolar signal to generate a PWM output signal. A first charge pump is connected to the secondary winding responsive to the PWM output signal to generate a level shifted PWM output signal. A second charge pump is connected to the secondary winding to generate a readjusted PWM output signal by decreasing at least a portion of the level shifted PWM output signal. A gate switching device is connected to the first charge pump and second charge pump. A level shifted PWM output signal establishes an ON condition and the readjusted PWM output signal establishes an OFF condition of the gate MOSFET.
    Type: Application
    Filed: January 23, 2017
    Publication date: August 23, 2018
    Inventors: Sriram Chandrasekaran, Michael S. Hockema
  • Patent number: 9736219
    Abstract: Methods, systems, and computer-readable media for managing open shares in an enterprise computing environment are presented. In some embodiments, a computer system may receive a request to scan one or more servers for open shares. Then, the computer system may validate one or more input files associated with the request and verify access to the one or more servers. Next, the computer system may scan the one or more servers to create a runtime share list file identifying one or more open shares. Subsequently, the computer system may identify at least one open share to be remediated and may apply one or more remediation actions to the at least one open share. Thereafter, the computer system may update an output file to include remediation information identifying the one or more remediation actions applied to the at least one open share and may send the output file.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: August 15, 2017
    Assignee: Bank of America Corporation
    Inventors: Chirag Kansagra, William O'Callaghan, Minesh Shah, Ketankumar Modi, Mubarak Chanbaig, Ritesh Pandey, Sriram Chandrasekaran
  • Publication number: 20160381117
    Abstract: Methods, systems, and computer-readable media for managing open shares in an enterprise computing environment are presented. In some embodiments, a computer system may receive a request to scan one or more servers for open shares. Then, the computer system may validate one or more input files associated with the request and verify access to the one or more servers. Next, the computer system may scan the one or more servers to create a runtime share list file identifying one or more open shares. Subsequently, the computer system may identify at least one open share to be remediated and may apply one or more remediation actions to the at least one open share. Thereafter, the computer system may update an output file to include remediation information identifying the one or more remediation actions applied to the at least one open share and may send the output file.
    Type: Application
    Filed: June 26, 2015
    Publication date: December 29, 2016
    Inventors: Chirag Kansagra, William O'Callaghan, Minesh Shah, Ketankumar Modi, Mubarak Chanbaig, Ritesh Pandey, Sriram Chandrasekaran
  • Patent number: 9379629
    Abstract: A magnetic device and power converter employing the same. In one embodiment, the magnetic device includes a first L-core segment including a first leg and a second leg extending therefrom, and an opposing second L-core segment including a first leg and a second leg extending therefrom. The magnetic device also includes a winding formed around at least one of the first leg and the second leg of the first L-core segment or the second L-core segment.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: June 28, 2016
    Assignee: Power Systems Technologies, Ltd.
    Inventor: Sriram Chandrasekaran
  • Patent number: 9240712
    Abstract: A controller for a power converter includes a current-sense device couplable in series with switched terminals of power switches of interleaved switching regulators and configured to produce a current-sense signal. The controller also includes an error amplifier configured to produce an error signal as a function of a characteristic of the power converter. The controller also includes a duty-cycle controller configured to sample the current-sense signal at mid-points of duty cycles of the power switches and regulate the characteristic as a function of the error signal and the current-sense signal.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: January 19, 2016
    Assignee: Power Systems Technologies Ltd.
    Inventor: Sriram Chandrasekaran