Abstract: Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on top and bottom sides of a monolithic structure can facilitate the formation of wrap-around plated terminations.

Abstract: Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on top and bottom sides of a monolithic structure can facilitate the formation of wrap-around plated terminations.

Abstract: Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on top and bottom sides of a monolithic structure can facilitate the formation of wrap-around plated terminations.

Abstract: Improved method steps for making a multilayer electronic components are disclosed. Monolithic components are formed with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. Electrodes and insulating substrates are provided in an interleaved arrangement and selected portions of the electrodes are exposed along selected edges of the substrates. Anchor tabs, which are not in direct contact with the electrodes and offer additional nucleation points for plated structures, may also optionally be provided and exposed in some embodiments.

Abstract: Improved method steps for making a multilayer electronic components are disclosed. Monolithic components are formed with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. Electrodes and insulating substrates are provided in an interleaved arrangement and selected portions of the electrodes are exposed along selected edges of the substrates. Anchor tabs, which are not in direct contact with the electrodes and offer additional nucleation points for plated structures, may also optionally be provided and exposed in some embodiments.

Abstract: Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on top and bottom sides of a monolithic structure can facilitate the formation of wrap-around plated terminations.

Abstract: Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on top and bottom sides of a monolithic structure can facilitate the formation of wrap-around plated terminations.

Abstract: Methods of fabricating an array capacitor are disclosed, in which via structures of the array capacitor have increased uniformity in their transverse areas. One method involves perforating a capacitor body to form first holes extending from a first surface and partially through the capacitor body. The capacitor body may be further perforated to form second holes extending from a second opposed surface of the capacitor body. The second holes are to connect to the first holes to provide through holes extending across a thickness of the capacitor body. An appropriate conductive material may then be filled in the through holes to form via structures with increased uniformity in their transverse areas.

Abstract: Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on top and bottom sides of a monolithic structure can facilitate the formation of wrap-around plated terminations.

Abstract: A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.

Abstract: Methods of fabricating an array capacitor are disclosed, in which via structures of the array capacitor have increased uniformity in their transverse areas. One method involves perforating a capacitor body to form first holes extending from a first surface and partially through the capacitor body. The capacitor body may be further perforated to form second holes extending from a second opposed surface of the capacitor body. The second holes are to connect to the first holes to provide through holes extending across a thickness of the capacitor body. An appropriate conductive material may then be filled in the through holes to form via structures with increased uniformity in their transverse areas.

Abstract: A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.

Abstract: Methods of fabricating an array capacitor are disclosed, in which via structures of the array capacitor have increased uniformity in their transverse areas. One method involves perforating a capacitor body to form first holes extending from a first surface and partially through the capacitor body. The capacitor body may be further perforated to form second holes extending from a second opposed surface of the capacitor body. The second holes are to connect to the first holes to provide through holes extending across a thickness of the capacitor body. An appropriate conductive material may then be filled in the through holes to form via structures with increased uniformity in their transverse areas.

Abstract: A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.

Abstract: A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.

Abstract: In some embodiments, an individual sub-assembly containing a ceramic interposer, silicon voltage regulator, and array capacitor is presented. In this regard, an apparatus is introduced having a table-shaped ceramic interposer containing conductive traces, a silicon voltage regulator coupled with contacts on a first surface of the ceramic interposer, and an array capacitor coupled with contacts on a second surface of the ceramic interposer. Other embodiments are also disclosed and claimed.

Abstract: Methods of fabricating an array capacitor are disclosed, in which via structures of the array capacitor have increased uniformity in their transverse areas. One method involves perforating a capacitor body to form first holes extending from a first surface and partially through the capacitor body. The capacitor body may be further perforated to form second holes extending from a second opposed surface of the capacitor body. The second holes are to connect to the first holes to provide through holes extending across a thickness of the capacitor body. An appropriate conductive material may then be filled in the through holes to form via structures with increased uniformity in their transverse areas.

Abstract: A Multi-layer Ceramic Capacitor (MLCC) device of a low self-inductance is disclosed. The MLCC device includes a plurality of ceramic sheets arranged in parallel to each other, a plurality of inner metal electrodes, and a plurality of outer electrodes including a pair of positive terminals and a pair of negative terminals. The plurality of inner metal electrodes and the plurality of ceramic sheets are stacked alternately to form a plurality of capacitors. The plurality of outer electrodes is disposed on corners of the plurality of ceramic sheets such that the pair of positive terminals is disposed on adjacent corners of the plurality of ceramic sheets and the pair of negative terminals is disposed on other set of adjacent corners of the plurality of ceramic sheets. An MLCC device having the plurality of outer electrodes disposed on middle portions of the edges of the plurality of ceramic sheets is also disclosed.

Abstract: In some embodiments, an array capacitor for decoupling multiple voltages is presented. In this regard, an array capacitor is introduced having two electrically isolated capacitor regions. Other embodiments are also disclosed and claimed.

Abstract: In some embodiments, a ceramic interposer with silicon voltage regulator and array capacitor combination for integrated circuit packages is presented. In this regard, an apparatus is introduced having a bowl-shaped ceramic interposer containing conductive traces, one or more silicon voltage regulator(s) coupled with contacts on a first surface of the ceramic interposer, and one or more array capacitor(s) coupled with contacts on a second surface of the ceramic interposer. Other embodiments are also disclosed and claimed.