Abstract: A method, system and computer readable medium are provided for software defect reduction. To perform the software defect reduction implementation parameters for a software application in a development phase are collected, and an Extract, Transform and Load (ETL) is performed. The ETL analyzes data from one or more databases based on the implementation parameters to obtain relevant implementation data. The one or more databases store implementation data related to previously developed software applications, and the relevant implementation data is data stored in the one or more databases that is data that is relevant to the implementation parameters. The relevant implementation data is then summarized to obtain predicted data relevant to the software application in the development phase.

Abstract: This application discusses techniques for providing a power-on reset (POR) circuit. The techniques take advantage of the small size of active devices, consume very little current and can use a native NMOS transistor to provide a stable reference over temperature and voltage variations.

Abstract: An embodiment of the disclosure provides a method of integrating data across multiple data stores in a smart cache in order to provide data to one or more recipient systems. The method includes automatically ingesting diverse data from multiple data sources, automatically reconciling the ingested diverse data by updating semantic models based on the ingested diverse data, storing the ingested diverse data based on one or more classification of the data sources according to the semantic models, automatically generating scalable service endpoints which are semantically consistent according to the classification of the data sources, and responding to a call from the one or more recipient systems by providing data in the classification of the data sources.

Abstract: Embodiments of the disclosure provide a method for aggregating and providing health data records to an electronic device. The method is performed by a server that includes a processor and a non-transitory computer readable medium with processor-executable instructions stored thereon. When the instructions are executed by the processor, the server performs the method including: (a) receiving collected data from one or more client devices, the collected data comprising health related data including at least one of step count data, heart rate data, sleep sensor data; (b) extracting metadata from the collected data; (c) pseudonymizing the collected data; (d) categorizing the collected data using the extracted metadata and enterprise ontology of the server; and (e) storing the collected data.

Abstract: A regulator circuit can include a cascaded topology, comprising a first integrated low-dropout (LDO) regulator circuit having a supply node, the first integrated LDO regulator circuit configured to provide a first loop bandwidth and configured to provide a regulated first output voltage to an intermediate node using energy provided by the supply node, and a second integrated LDO regulator circuit having an input coupled to the intermediate node, the second LDO regulator circuit configured to provide a second loop bandwidth and configured to provide a regulated second output voltage to an output node, where the second loop bandwidth is narrower than the first loop bandwidth. The regulator circuit need not require an external capacitor. The regulator circuit can be used to provide one or more of enhanced power supply rejection and noise performance.

Abstract: A regulator circuit can include a cascaded topology, comprising a first integrated low-dropout (LDO) regulator circuit having a supply node, the first integrated LDO regulator circuit configured to provide a first loop bandwidth and configured to provide a regulated first output voltage to an intermediate node using energy provided by the supply node, and a second integrated LDO regulator circuit having an input coupled to the intermediate node, the second LDO regulator circuit configured to provide a second loop bandwidth and configured to provide a regulated second output voltage to an output node, where the second loop bandwidth is narrower than the first loop bandwidth. The regulator circuit need not require an external capacitor. The regulator circuit can be used to provide one or more of enhanced power supply rejection and noise performance.

Abstract: A relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation includes a first current source that generates charging current, a second current source coupled to the first current source to generate reference voltage, a resistor coupled to the second current source to enable generation of the reference voltage, a capacitor coupled to the first current source that is charged based on the charging current, a comparator responsive to voltage corresponding to the capacitor and the reference voltage to generate output voltage, a peak detector coupled to the capacitor to generate peak voltage, an error detector coupled to the peak detector and the second current source to generate an error based on the peak voltage and the reference voltage, and a controller coupled to the error detector to control one of the charging current, offset voltage input to the comparator, and capacitance of the capacitor.

Abstract: A relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation includes a first current source that generates charging current, a second current source coupled to the first current source to generate reference voltage, a resistor coupled to the second current source to enable generation of the reference voltage, a capacitor coupled to the first current source that is charged based on the charging current, a comparator responsive to voltage corresponding to the capacitor and the reference voltage to generate output voltage, a peak detector coupled to the capacitor to generate peak voltage, an error detector coupled to the peak detector and the second current source to generate an error based on the peak voltage and the reference voltage, and a controller coupled to the error detector to control one of the charging current, offset voltage input to the comparator, and capacitance of the capacitor.

Abstract: A Delay Locked Loop (DLL) and method for generating multiple equally spaced phases over a wide frequency range is disclosed. The DLL includes a delay line, and a control module. The delay line receives a reference clock signal and outputs a final delay clock signal in response to the reference clock signal. The delay line includes a plurality of delay cells connected in series. The plurality of delay cells generate a plurality of delay clock signals having equally spaced phases. The control module generates a phase control signal based on counting a number of pulses of the reference clock signal that are input to the delay line before occurrence of a first corresponding pulse of the final delay clock signal.