Patents by Inventor Sriram Govindan

Sriram Govindan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11231852
    Abstract: In the embodiment a determination is made, for one or more applications being executed by the computing system, of an amount of the first or second memory being used by the one or more applications. Based on the determination, a portion of the memory resources of the third memory are configured to function with the first or second memory when it is determined that the amount of the first or second memory being used by the one or more applications is not sufficient for the memory needs of the one or more applications and a portion of the memory resources of the third memory are removed from functioning with the first or second memory when it is determined that the amount of the first or second memory being used by the one or more applications is more than is needed for the memory needs of the one or more applications.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: January 25, 2022
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Anirudh Badam, Sriram Govindan, Bikash Sharma, Badriddine Khessib, Iyswarya Narayanan, Aishwarya Ganesan
  • Patent number: 11011768
    Abstract: A fuel cell power controller tracks load current and fuel cell output voltage, and alerts on excessive fuel cell ramp rate, so another power source can supplement the fuel cell and/or the load can be reduced. A power engineering process makes efficient use of available fuel cell power by ramping up power flow rapidly when power is available, while respecting the ramp rate and other power limitations of the fuel cell and safety limitations of the load. Power flow decreases after an alert indicating an electrical output limitation of the fuel cell. Permitted power flow increases in response to a power demand increase (actual or requested) from the load in the absence of the alert. Power flow may increase or decrease in a fixed amount, a proportional amount, or per a sequence. A power controller relay may trip open on a low fuel cell output voltage or high load current.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: May 18, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Di Wang, Sriram Govindan, John J. Siegler, Jie Liu, Ricardo Bianchini, Eric Peterson, Sean M. James, Bryan Kelly
  • Patent number: 10936038
    Abstract: A computing device may comprise a volatile memory and a non-volatile storage device. Upon system shutdown, contents of the volatile memory may be preserved by memory transfer operations from the volatile memory to the non-volatile storage device. During memory preservation, the computing device may enter a low-power state. The low-power state may comprise suspension of power to a core of a processor while maintaining power to the processor's uncore, and disablement of interrupt signals not related to memory transfer operations. Power delivery to the core of the processor may be periodically resumed to initiate additional memory transfer operations.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: March 2, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Bryan Kelly, Mark Santaniello, Sriram Govindan, Anirudh Badam
  • Patent number: 10594784
    Abstract: Disaster recovery is provided for an application that is being hosted on a current data center, thus ensuring the availability of the application. An option for replicating session state data for the application is selected. This selection is made from a set of different session state data replication options each of which has different performance and resource cost trade-offs. The selected option determines how the session state data for the application is to be replicated. The selected option is implemented, where the implementation results in the session state data for the application being replicated outside of the current data center, thus ensuring that this data remains available in the event that the current data center goes offline.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: March 17, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Aman Kansal, Sriram Govindan
  • Patent number: 10528113
    Abstract: Technology for handling overcurrent conditions on electrical circuits that power multiple computing modules is disclosed. Aspects of the technology include a power system adapted to provide notifications of overcurrent conditions, and computing modules adapted to reduce an operating speed thereof in response to notification of an overcurrent condition.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: January 7, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Bryan D. Kelly, Badriddine Khessib, Sriram Govindan
  • Publication number: 20190324516
    Abstract: A computing device may comprise a volatile memory and a non-volatile storage device. Upon system shutdown, contents of the volatile memory may be preserved by memory transfer operations from the volatile memory to the non-volatile storage device. During memory preservation, the computing device may enter a low-power state. The low-power state may comprise suspension of power to a core of a processor while maintaining power to the processor's uncore, and disablement of interrupt signals not related to memory transfer operations. Power delivery to the core of the processor may be periodically resumed to initiate additional memory transfer operations.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 24, 2019
    Inventors: Bryan Kelly, Mark Santaniello, Sriram Govindan, Anirudh Badam
  • Patent number: 10359826
    Abstract: A computing device may comprise a processor, a volatile memory and a non-volatile storage device. An operating system or firmware of the device may cause one or more pages of the volatile memory to be treated, by applications executing on the computing device, as non-volatile memory pages. A maximum number of pages that may be treated as non-volatile may be determined based on an amount of energy available in a battery and an amount of energy needed to transfer a page of memory to the non-volatile storage device.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: July 23, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Bryan D. Kelly, Mark A. Santaniello, Sriram Govindan, Anirudh Badam
  • Patent number: 10338659
    Abstract: A computing device may comprise a volatile memory and a non-volatile storage device. Upon system shutdown, contents of the volatile memory may be preserved by memory transfer operations from the volatile memory to the non-volatile storage device. During memory preservation, the computing device may enter a low-power state. The low-power state may comprise suspension of power to a core of a processor while maintaining power to the processor's uncore, and disablement of interrupt signals not related to memory transfer operations. Power delivery to the core of the processor may be periodically resumed to initiate additional memory transfer operations.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: July 2, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Bryan Kelly, Mark Santaniello, Sriram Govindan, Anirudh Badam
  • Publication number: 20190187897
    Abstract: In the embodiment a determination is made, for one or more applications being executed by the computing system, of an amount of the first or second memory being used by the one or more applications. Based on the determination, a portion of the memory resources of the third memory are configured to function with the first or second memory when it is determined that the amount of the first or second memory being used by the one or more applications is not sufficient for the memory needs of the one or more applications and a portion of the memory resources of the third memory are removed from functioning with the first or second memory when it is determined that the amount of the first or second memory being used by the one or more applications is more than is needed for the memory needs of the one or more applications.
    Type: Application
    Filed: December 18, 2017
    Publication date: June 20, 2019
    Inventors: Anirudh Badam, Sriram Govindan, Bikash Sharma, Badriddine Khessib, Iyswarya Narayanan, Aishwarya Ganesan
  • Publication number: 20190123368
    Abstract: A fuel cell power controller tracks load current and fuel cell output voltage, and alerts on excessive fuel cell ramp rate, so another power source can supplement the fuel cell and/or the load can be reduced. A power engineering process makes efficient use of available fuel cell power by ramping up power flow rapidly when power is available, while respecting the ramp rate and other power limitations of the fuel cell and safety limitations of the load. Power flow decreases after an alert indicating an electrical output limitation of the fuel cell. Permitted power flow increases in response to a power demand increase (actual or requested) from the load in the absence of the alert. Power flow may increase or decrease in a fixed amount, a proportional amount, or per a sequence. A power controller relay may trip open on a low fuel cell output voltage or high load current.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Inventors: Di WANG, Sriram GOVINDAN, John J. SIEGLER, Jie LIU, Ricardo BIANCHINI, Eric PETERSON, Sean M. JAMES, Bryan KELLY
  • Patent number: 10255113
    Abstract: Architecture that facilitates the estimation of interference among workloads (e.g., virtual machines) due to sharing of a shared resource (e.g., a shared cache of a computer processor), and optimization of a desired performance objective such as power or energy use in the presence of the interference. Estimation is to the extent of interference by characterizing the nature of shared resource usage and its effect on performance. Performance optimization is accomplished using metrics based on the above estimation, or alternatively, an explicit measurement of the interference effects. Methods are employed to estimate interference on the workload's performance with changes in availability of the shared resource or with combinations of other workloads sharing the same resource and allocating workloads to one or more physical computers or resources to workloads such that a desired performance objective is optimized. The methods can include allocating workloads on demand.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: April 9, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sriram Govindan, Jie Liu, Aman Kansal
  • Patent number: 10199669
    Abstract: A fuel cell power controller tracks load current and fuel cell output voltage, and alerts on excessive fuel cell ramp rate, so another power source can supplement the fuel cell and/or the load can be reduced. A power engineering process makes efficient use of available fuel cell power by ramping up power flow rapidly when power is available, while respecting the ramp rate and other power limitations of the fuel cell and safety limitations of the load. Power flow decreases after an alert indicating an electrical output limitation of the fuel cell. Permitted power flow increases in response to a power demand increase (actual or requested) from the load in the absence of the alert. Power flow may increase or decrease in a fixed amount, a proportional amount, or per a sequence. A power controller relay may trip open on a low fuel cell output voltage or high load current.
    Type: Grant
    Filed: May 1, 2016
    Date of Patent: February 5, 2019
    Assignee: Micrsoft Technology Licensing, LLC
    Inventors: Di Wang, Sriram Govindan, John J. Siegler, Jie Liu, Ricardo Bianchini, Eric Peterson, Sean M. James, Bryan Kelly
  • Patent number: 10168756
    Abstract: Various techniques for managing power backup for computing devices are disclosed herein. In one embodiment, a method includes receiving data representing a backup capacity of one or more backup power units and data representing a backup power profile of one or more processing units sharing the one or more backup power units. A portion of the backup capacity may then be assigned to each of the one or more processing units based at least in part on both the received data representing the backup capacity of the one or more backup power units and the received data representing the profile of the one or more processing units.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: January 1, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Badriddine Khessib, Bryan Kelly, Mark Santaniello, Chris Ong, John Siegler, Sriram Govindan, Shaun Harris
  • Patent number: 10078455
    Abstract: Aspects extend to methods, systems, and computer program products for predicting solid state drive reliability. Aspects of the invention can be used to predict and/or to configure a data center to minimize one or more of: SSD capacity degradation (how much storage an SSD has left), SSD performance degradation (reduced read/write latency/throughput), and SSD failure. Models and data center considerations can be based on device level SSD related operations, such as, for example, read, write, erase. Operations decisions can be made for a data center based on SSD specific features, such as, for example, remaining capacity, write amplification factor, etc. Dependence and/or causality of various different data center factors can be leveraged. The impact of the various data center factors on different SSD failure modes and capacity/performance degradation can be quantified to drive SSD design, SSD provisioning, and SSD operations.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: September 18, 2018
    Inventors: Iyswarya Narayanan, Di Wang, Myeongjae Jeon, Bikash Sharma, Laura Marie Caulfield, Sriram Govindan, Benjamin Franklin Cutler, Christopher W. Hoder, Jaya Naga Satish Bobba, Jie Liu, Badriddine Khessib
  • Patent number: 10031801
    Abstract: Technology relating to configurable reliability schemes for memory devices is disclosed. The technology includes a memory controller that selectively controls at least a type or an extent of a reliability scheme for at least a portion of a memory device. The technology also includes a computing device that can dynamically select and employ reliability schemes from a collection of different reliability schemes. A reliability scheme may be selected on a per-process, per-allocation request, per-page, per-cache-line, or other basis. The reliability schemes may include use of parity, use of data mirroring, use of an error correction code (ECC), storage of data without redundancy, etc.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: July 24, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sriram Govindan, Bryan Kelly
  • Patent number: 10007579
    Abstract: Embodiments of memory backup management in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method of managing memory backup includes in response to a system error being detected, causing a memory controller to disengage from communicating with and controlling a hybrid memory device having a volatile memory module and a non-volatile memory module. The method can also include causing the hybrid memory device to copy data from the volatile memory module to the non-volatile memory module subsequent to disengaging the memory controller communicating with and controlling the storage device and without operating the main processor and the memory controller.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: June 26, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Mark A. Shaw, Scott Chao-Chueh Lee, Sriram Govindan, Bryan Kelly
  • Publication number: 20180107596
    Abstract: Embodiments of battery-based data persistence management in computing devices are disclosed therein. In one embodiment, a method includes receiving a storage request to persistently store data in the computing device. In response to receiving the storage request, the method includes allocating a number of memory blocks of the main memory to store the data associated with the storage request and incrementing an accumulated number of memory blocks in the main memory that contain data stored in response to received storage requests. The method further includes maintaining the accumulated number of memory blocks in the main memory below a threshold corresponding to an energy capacity of the auxiliary power source and copying all of the stored data in the memory blocks of the main memory to the persistent storage using power from only the auxiliary power source when the main power supply suffers an unexpected power failure.
    Type: Application
    Filed: January 16, 2017
    Publication date: April 19, 2018
    Inventors: Bryan Kelly, Bikash Sharma, Anirudh Badam, Sriram Govindan, Rajat Kateja
  • Publication number: 20180067537
    Abstract: Technology for handling overcurrent conditions on electrical circuits that power multiple computing modules is disclosed. Aspects of the technology include a power system adapted to provide notifications of overcurrent conditions, and computing modules adapted to reduce an operating speed thereof in response to notification of an overcurrent condition.
    Type: Application
    Filed: November 13, 2017
    Publication date: March 8, 2018
    Inventors: Bryan D. Kelly, Badriddine Khessib, Sriram Govindan
  • Publication number: 20170364134
    Abstract: A computing device may comprise a volatile memory and a non-volatile storage device. Upon system shutdown, contents of the volatile memory may be preserved by memory transfer operations from the volatile memory to the non-volatile storage device. During memory preservation, the computing device may enter a low-power state. The low-power state may comprise suspension of power to a core of a processor while maintaining power to the processor's uncore, and disablement of interrupt signals not related to memory transfer operations. Power delivery to the core of the processor may be periodically resumed to initiate additional memory transfer operations.
    Type: Application
    Filed: August 1, 2017
    Publication date: December 21, 2017
    Inventors: Bryan Kelly, Mark Santaniello, Sriram Govindan, Anirudh Badam
  • Publication number: 20170329379
    Abstract: A computing device may comprise a processor, a volatile memory and a non-volatile storage device. An operating system or firmware of the device may cause one or more pages of the volatile memory to be treated, by applications executing on the computing device, as non-volatile memory pages. A maximum number of pages that may be treated as non-volatile may be determined based on an amount of energy available in a battery and an amount of energy needed to transfer a page of memory to the non-volatile storage device.
    Type: Application
    Filed: July 28, 2017
    Publication date: November 16, 2017
    Inventors: Bryan D. Kelly, Mark A. Santaniello, Sriram Govindan, Anirudh Badam