Patents by Inventor Sriram Haridas
Sriram Haridas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8861358Abstract: In one embodiment, a router that accesses a cable network through a cable modem receives, from the cable modem, a plurality of service-flow classifications utilized by the cable modem to describe service flows on the cable network. Based on the received service-flow classifications from the cable modem, the router determines traffic destined for the cable network that corresponds to each service-flow on the cable network. The router receives, from the cable modem, an indication of network backpressure for a particular service-flow on the cable network. The indication of network backpressure is received when a threshold of network backpressure has been surpassed for the particular service-flow on the cable network. The router controls particular traffic that corresponds to the particular service-flow on the cable network based on the indication of network backpressure for the particular service-flow on the cable network.Type: GrantFiled: April 14, 2011Date of Patent: October 14, 2014Assignee: Cisco Technology, Inc.Inventors: Kenneth J. Croft, Jr., Sriram Haridas, John B. Duffie, III
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Patent number: 8599855Abstract: Techniques for routing a payload of a first network protocol, which includes header information for a second network protocol, include communicating a packet. In a circuit block, a first type for the first network protocol and a second type for the second network protocol are determined. The circuit block stores a classification that indicates a unique combination of the first type and the second type. A general purpose processor routes the packet based on the classification. Processor clock cycles are saved that would be consumed in determining the types. Furthermore, based on the classification, the processor can store an offset value for aligning the header relative to a cache line. The circuit block can store the packet shifted by the offset value. The processor can then retrieve from memory a single cache line to receive the header, thereby saving excess loading and ejecting of cache.Type: GrantFiled: November 16, 2010Date of Patent: December 3, 2013Assignee: Cisco Technology, Inc.Inventors: William Lee, Michael Wright, Joydeep Chowdhury, Sriram Haridas, Martin Hughes
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Publication number: 20110194411Abstract: In one embodiment, a router that accesses a cable network through a cable modem receives, from the cable modem, a plurality of service-flow classifications utilized by the cable modem to describe service flows on the cable network. Based on the received service-flow classifications from the cable modem, the router determines traffic destined for the cable network that corresponds to each service-flow on the cable network. The router receives, from the cable modem, an indication of network backpressure for a particular service-flow on the cable network. The indication of network backpressure is received when a threshold of network backpressure has been surpassed for the particular service-flow on the cable network. The router controls particular traffic that corresponds to the particular service-flow on the cable network based on the indication of network backpressure for the particular service-flow on the cable network.Type: ApplicationFiled: April 14, 2011Publication date: August 11, 2011Applicant: CISCO TECHNOLOGY, INC.Inventors: Kenneth J. Croft, JR., Sriram Haridas, John B. Duffie, III
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Patent number: 7948883Abstract: In one embodiment, a cable modem determines network backpressure per service-flow, and transmits the network backpressure per service-flow to a router (e.g., co-located on a same network device). Also, the cable modem may transmit service-flow classifications to the router, such that the router may then control traffic per service-flow based on the network backpressure per service-flow, accordingly.Type: GrantFiled: July 12, 2007Date of Patent: May 24, 2011Assignee: Cisco Technology, Inc.Inventors: Kenneth J. Croft, Jr., Sriram Haridas, John B. Duffie, III
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Publication number: 20110064081Abstract: Techniques for routing a payload of a first network protocol, which includes header information for a second network protocol, include communicating a packet. In a circuit block, a first type for the first network protocol and a second type for the second network protocol are determined. The circuit block stores a classification that indicates a unique combination of the first type and the second type. A general purpose processor routes the packet based on the classification. Processor clock cycles are saved that would be consumed in determining the types. Furthermore, based on the classification, the processor can store an offset value for aligning the header relative to a cache line. The circuit block can store the packet shifted by the offset value. The processor can then retrieve from memory a single cache line to receive the header, thereby saving excess loading and ejecting of cache.Type: ApplicationFiled: November 16, 2010Publication date: March 17, 2011Applicant: Cisco Technology, Inc.Inventors: William Lee, Michael Wright, Joydeep Chowdhury, Sriram Haridas, Martin Hughes
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Patent number: 7848332Abstract: Techniques for routing a payload of a first network protocol, which includes header information for a second network protocol, include communicating a packet. In a circuit block, a first type for the first network protocol and a second type for the second network protocol are determined. The circuit block stores a classification that indicates a unique combination of the first type and the second type. A general purpose processor routes the packet based on the classification. Processor clock cycles are saved that would be consumed in determining the types. Furthermore, based on the classification, the processor can store an offset value for aligning the header relative to a cache line. The circuit block can store the packet shifted by the offset value. The processor can then retrieve from memory a single cache line to receive the header, thereby saving excess loading and ejecting of cache.Type: GrantFiled: November 15, 2004Date of Patent: December 7, 2010Assignee: Cisco Technology, Inc.Inventors: William Lee, Michael Wright, Joydeep Chowdhury, Sriram Haridas, Martin Hughes
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Patent number: 7464243Abstract: Techniques for initializing an arbitrary portion of memory with an arbitrary pattern includes using a memory controller for performing sequenced read and write operations. The memory controller receives address data, length data and pattern data on a data bus connected to a processor. The address data indicates a location in memory. The length data indicates an amount of memory to be initialized. The pattern data indicates a particular series of bits that is much shorter than the amount of memory indicated by the length data. The memory controller performs multiple write operations on memory beginning at a first location based on the address data and ending at a second location based on the length data. Each write operation writes the pattern data to a current location in memory, thereby initializing the arbitrary portion of memory with an arbitrary pattern based on the pattern data.Type: GrantFiled: December 21, 2004Date of Patent: December 9, 2008Assignee: Cisco Technology, Inc.Inventors: Sriram Haridas, Martin Hughes, William Lee, John Mitten
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Patent number: 7284050Abstract: A method and system for a voice multicast hardware accelerator are disclosed in which a network device or system includes a host system coupled to a memory to store data and a line card to interface with a plurality of user devices. The host system is to receive a network packet including voice data, to store the voice data in the memory, and to send a voice packet related to the voice data to the line card without duplication. The voice packet includes descriptor fields for multicasting the voice data. The line card is to multicast selectively the voice data stored in the memory to the plurality of user devices based on the descriptor fields in the voice packet. A multicast hardware accelerator can be used to multicast selectively the voice data.Type: GrantFiled: March 26, 2001Date of Patent: October 16, 2007Assignee: Cisco Technology, Inc.Inventors: Sriram Haridas, Louis Couture
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Publication number: 20060136682Abstract: Techniques for initializing an arbitrary portion of memory with an arbitrary pattern includes using a memory controller for performing sequenced read and write operations. The memory controller receives address data, length data and pattern data on a data bus connected to a processor. The address data indicates a location in memory. The length data indicates an amount of memory to be initialized. The pattern data indicates a particular series of bits that is much shorter than the amount of memory indicated by the length data. The memory controller performs multiple write operations on memory beginning at a first location based on the address data and ending at a second location based on the length data. Each write operation writes the pattern data to a current location in memory, thereby initializing the arbitrary portion of memory with an arbitrary pattern based on the pattern data.Type: ApplicationFiled: December 21, 2004Publication date: June 22, 2006Inventors: Sriram Haridas, Martin Hughes, William Lee, John Mitten
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Publication number: 20060104268Abstract: Techniques for routing a payload of a first network protocol, which includes header information for a second network protocol, include communicating a packet. In a circuit block, a first type for the first network protocol and a second type for the second network protocol are determined. The circuit block stores a classification that indicates a unique combination of the first type and the second type. A general purpose processor routes the packet based on the classification. Processor clock cycles are saved that would be consumed in determining the types. Furthermore, based on the classification, the processor can store an offset value for aligning the header relative to a cache line. The circuit block can store the packet shifted by the offset value. The processor can then retrieve from memory a single cache line to receive the header, thereby saving excess loading and ejecting of cache.Type: ApplicationFiled: November 15, 2004Publication date: May 18, 2006Inventors: William Lee, Michael Wright, Joydeep Chowdhury, Sriram Haridas, Martin Hughes