Patents by Inventor Sriram Kotni

Sriram Kotni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for verification of multi-voltage circuit design
    Patent number: 8255859
    Abstract: Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.
    Type: Grant
    Filed: May 18, 2009
    Date of Patent: August 28, 2012
    Assignee: Synopsys, Inc.
    Inventors: Harsh Chilwal, Srikanth Jadcherla, Sriram Kotni, Prapanna Tiwari
  • Method and system for static verification of multi-voltage circuit design
    Patent number: 7694252
    Abstract: Verification of a design for a multi-voltage circuit which defines a plurality of iso-voltage rail blocks, and which comprises voltage state information for the iso-voltage-rail blocks. Verification includes generating cross-over information regarding a cross-over signal between two iso-voltage-rail blocks, identifying the voltage state relationship between the two iso-voltage-rail blocks based on the voltage state information, and verifying the validity of the cross-over signal based on the determined voltage state relationship.
    Type: Grant
    Filed: April 21, 2007
    Date of Patent: April 6, 2010
    Assignee: Synopsys, Inc.
    Inventors: Saptarshi Biswas, Srikanth Jadcherla, Sriram Kotni, Debabrata Bagchi
  • Automated design process and method for multi-rail cells and connections
    Patent number: 7694241
    Abstract: Automated design process and method with set of syntactic elements compensates for inability to represent voltage island connection of multi-rail cells in RTL source files in traditional design process which inhibits development of design automation methods and causes hardship and risk of failure to simulate, synthesize, perform physical design or formally verify a semiconductor chip design implemented with multi-rail.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: April 6, 2010
    Assignee: Synopsys, Inc.
    Inventors: Srikanth Jadcherla, Sriram Kotni
  • METHOD AND SYSTEM FOR VERIFICATION OF MULTI-VOLTAGE CIRCUIT DESIGN
    Publication number: 20090228852
    Abstract: Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.
    Type: Application
    Filed: May 18, 2009
    Publication date: September 10, 2009
    Applicant: SYNOPSYS, INC.
    Inventors: Harsh Chilwal, Srikanth Jadcherla, Sriram Kotni, Prapanna Tiwari
  • Method and system for verification of multi-voltage circuit design
    Patent number: 7546566
    Abstract: Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: June 9, 2009
    Assignee: Synopsys, Inc.
    Inventors: Harsh Chilwal, Srikanth Jadcherla, Sriram Kotni, Prapanna Tiwari
  • METHOD AND SYSTEM FOR VERIFICATION OF MULTI-VOLTAGE CIRCUIT DESIGN
    Publication number: 20080250364
    Abstract: Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.
    Type: Application
    Filed: April 5, 2007
    Publication date: October 9, 2008
    Inventors: Harsh Chilwal, Srikanth Jadcherla, Sriram Kotni, Prapanna Tiwari