Patents by Inventor Sriram Muthukumar

Sriram Muthukumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200054259
    Abstract: Systems, methods, and devices include a high-density analog multiplexer topology. Such topologies can be used, for example, in sensor device applications. An analog multiplexer circuit can include circuitry to receive N input signals; and circuitry to generate N selection signals for selecting one of said N data signals to be output from said analog multiplexer circuit. The analog multiplexer comprises one or more analog impedances.
    Type: Application
    Filed: August 16, 2019
    Publication date: February 20, 2020
    Applicant: EnLiSense, LLC
    Inventors: Devangsingh Gajendarsingh Sankhala, Sriram Muthukumar
  • Publication number: 20190250153
    Abstract: Disclosed herein are devices, apparatus, systems, methods and kits for performing immunoassay tests on a sample. The A sensing apparatus is provided for detecting a plurality of different target analytes in a sample. The apparatus may comprise an array of sensing devices provided on a substrate, each sensing device in the array comprising a working electrode having (1) semiconducting nanostructures disposed thereon and (2) a capture reagent coupled to the semiconducting nanostructures that selectively binds to a different target analyte in the sample. The apparatus may also comprise sensing circuitry that (1) simultaneously detects changes to electron and ion mobility and charge accumulation in the array of sensing devices when the capture reagents in the array of sensing devices selectively bind to the plurality of different target analytes, and (2) determines the presence and concentrations of the plurality of different target analytes in the sample based on the detected changes.
    Type: Application
    Filed: October 19, 2017
    Publication date: August 15, 2019
    Applicants: EnLiSense, LLC, Board of Regents, The University of Texas System
    Inventors: Sriram Muthukumar, Shalini Prasad
  • Publication number: 20190148275
    Abstract: A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 16, 2019
    Inventors: Sriram MUTHUKUMAR, Charles A. GEALER
  • Publication number: 20190069818
    Abstract: A biosensor device includes a porous substrate, where the substrate comprises semiconductor elements functionalized to conjugate with a particular analyte, the semiconductor elements are embedded within at least a portion of the substrate, and the substrate is to absorb fluid capable of carrying the particular analyte. The device further includes two or more electrodes attached to the substrate to correspond to the portion of the substrate, where the portion of the substrate further comprises Room-Temperature Ionic Liquid (RTIL).
    Type: Application
    Filed: September 6, 2018
    Publication date: March 7, 2019
    Inventors: Shalini Prasad, Sriram Muthukumar
  • Patent number: 10186480
    Abstract: A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: January 22, 2019
    Assignee: INTEL CORPORATION
    Inventors: Sriram Muthukumar, Charles A. Gealer
  • Patent number: 10134689
    Abstract: A wafer level package device and method are disclosed that include a warpage compensation metal adhered to a backside of a semiconductor wafer for minimizing warpage of the semiconductor wafer, where multiple metal features have been formed on the device side of the semiconductor substrate. The warpage compensation metal may include a copper film.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: November 20, 2018
    Assignee: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Vivek S. Sridharan, Amit S. Kelkar, Sriram Muthukumar
  • Patent number: 10006882
    Abstract: An example biosensor is provided and includes a semiconductor sensing element, a first electrode and a second electrode located on a first plane of the sensing element with a first electric field being applied thereacross, a third electrode located on a second plane of the sensing element parallel to and removed from the first plane with a second electric field being applied across the first electrode and the third electrode perpendicular to the first electric field, and a dielectric substrate having a first portion that constrains a fluid including an analyte on a surface of the sensing element, and a second portion that facilitates dielectric separation of the fluid from the electrodes. The mutually perpendicular electric fields facilitate adjusting a height of a fluid-sensor interface comprising an electrical double layer in the fluid enabling detection and characterization of the analyte.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: June 26, 2018
    Assignee: EnLiSense, LLC
    Inventors: Shalini Prasad, Sriram Muthukumar, Anjan Panneer Selvam
  • Patent number: 9806047
    Abstract: A wafer level package, electronic device including the wafer level package, and fabrication methods are described that include forming a cantilever pillar design as a portion of the wafer level package and/or a segmented solder connection for preventing and reducing connection stress and increasing board level reliability. In implementations, the wafer level device that employs example techniques in accordance with the present disclosure includes at least a section of a processed semiconductor wafer including at least one integrated circuit die, a first dielectric layer disposed on the processed semiconductor wafer, a first pillar, a second pillar formed on the first pillar, a second dielectric layer formed on the first dielectric layer and surrounding a portion of the first pillar and the second pillar, and at least one solder ball disposed on the second pillar.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: October 31, 2017
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Karthik Thambidurai, Peter R. Harper, Sriram Muthukumar, Arkadii V. Samoilov
  • Patent number: 9728515
    Abstract: This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: August 8, 2017
    Assignee: Intel Corporation
    Inventors: Rubayat Mahmud, Saikumar Jayaraman, Sriram Muthukumar
  • Publication number: 20160247774
    Abstract: This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.
    Type: Application
    Filed: May 4, 2016
    Publication date: August 25, 2016
    Inventors: Rubayat Mahmud, Saikumar Jayaraman, Sriram Muthukumar
  • Publication number: 20160146754
    Abstract: An example biosensor is provided and includes a semiconductor sensing element, a first electrode and a second electrode located on a first plane of the sensing element with a first electric field being applied thereacross, a third electrode located on a second plane of the sensing element parallel to and removed from the first plane with a second electric field being applied across the first electrode and the third electrode perpendicular to the first electric field, and a dielectric substrate having a first portion that constrains a fluid including an analyte on a surface of the sensing element, and a second portion that facilitates dielectric separation of the fluid from the electrodes. The mutually perpendicular electric fields facilitate adjusting a height of a fluid-sensor interface comprising an electrical double layer in the fluid enabling detection and characterization of the analyte.
    Type: Application
    Filed: November 20, 2015
    Publication date: May 26, 2016
    Inventors: Shalini Prasad, Sriram Muthukumar, Anjan Panneer Selvam
  • Patent number: 9349698
    Abstract: This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: May 24, 2016
    Assignee: Intel Corporation
    Inventors: Rubayat Mahmud, Saikumar Jayaraman, Sriram Muthukumar
  • Publication number: 20150279799
    Abstract: A wafer level package, electronic device including the wafer level package, and fabrication methods are described that include forming a cantilever pillar design as a portion of the wafer level package and/or a segmented solder connection for preventing and reducing connection stress and increasing board level reliability. In implementations, the wafer level device that employs example techniques in accordance with the present disclosure includes at least a section of a processed semiconductor wafer including at least one integrated circuit die, a first dielectric layer disposed on the processed semiconductor wafer, a first pillar, a second pillar formed on the first pillar, a second dielectric layer formed on the first dielectric layer and surrounding a portion of the first pillar and the second pillar, and at least one solder ball disposed on the second pillar.
    Type: Application
    Filed: September 22, 2014
    Publication date: October 1, 2015
    Inventors: Karthik Thambidurai, Peter R. Harper, Sriram Muthukumar, Arkadii V. Samoilov
  • Patent number: 8860205
    Abstract: Embodiments of the present invention relate to a method of stiffening a semiconductor coreless package substrate to improve rigidity and resistance against warpage. An embodiment of the method comprises disposing a sacrificial mask on a plurality of contact pads on a second level interconnect (package-to-board interconnect) side of a coreless package substrate, forming a molded stiffener around the sacrificial mask without increasing the effective thickness of the substrate, and removing the sacrificial mask to form a plurality of cavities in the molded stiffener corresponding to the contact pads. Embodiments also include plating the surface of the contact pads and the sidewalls of the cavities in the molded cavities with an electrically conductive material.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: October 14, 2014
    Assignee: Intel Corporation
    Inventors: Sriram Muthukumar, Nicholas R. Watts, John S. Guzek
  • Publication number: 20140001631
    Abstract: This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.
    Type: Application
    Filed: June 27, 2012
    Publication date: January 2, 2014
    Inventors: Rubayat Mahmud, Saikumar Jayaraman, Sriram Muthukumar
  • Patent number: 8502400
    Abstract: A dam stiffener for a package substrate is presented. In an embodiment, the dam stiffener comprises a thermally curable polymer, and is simultaneously cured with the underfill material to act as stiffener to the substrate. In another embodiment, a curable reservoir material can be dispensed to fill the space between the integrated circuit die and the dam stiffener, forming a thick reservoir layer, acting as an additional stiffener for the package substrate.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: August 6, 2013
    Assignee: Intel Corporation
    Inventors: Prasanna Karpur, Sriram Muthukumar
  • Publication number: 20130127054
    Abstract: A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer.
    Type: Application
    Filed: January 14, 2013
    Publication date: May 23, 2013
    Inventors: Sriram MUTHUKUMAR, Charles A. GEALER
  • Patent number: 8387240
    Abstract: In one embodiment, a method includes forming a plurality of vias partially through a body, the vias including sidewalls defined by the body. An electrically insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer in the vias and on the upper surface, the electrically conductive layer defining first metal pads on the upper surface and second metal pads in contact with the first metal pads, the second metal pads having a denser pitch than the first metal pads. A dielectric layer is formed between adjacent first metal pads and between adjacent second metal pads. The body is thinned through a lower surface and the electrically insulating layer in the vias is exposed. After the thinning, a portion of the electrically insulating layer in the, vias is removed. The body is coupled to a substrate.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: March 5, 2013
    Assignee: Intel Corporation
    Inventors: Sriram Muthukumar, Raul Mancera, Yoshihiro Tomita, Chi-won Hwang
  • Publication number: 20120187583
    Abstract: A dam stiffener for a package substrate is presented. In an embodiment, the dam stiffener comprises a thermally curable polymer, and is simultaneously cured with the underfill material to act as stiffener to the substrate. In another embodiment, a curable reservoir material can be dispensed to fill the space between the integrated circuit die and the dam stiffener, forming a thick reservoir layer, acting as an additional stiffener for the package substrate.
    Type: Application
    Filed: March 6, 2012
    Publication date: July 26, 2012
    Applicant: Intel Corporation
    Inventors: Prasanna Karpur, Sriram Muthukumar
  • Patent number: 8143110
    Abstract: A dam stiffener for a package substrate is presented. In an embodiment, the dam stiffener comprises a thermally curable polymer, and is simultaneously cured with the underfill material to act as stiffener to the substrate. In another embodiment, a curable reservoir material can be dispensed to fill the space between the integrated circuit die and the dam stiffener, forming a thick reservoir layer, acting as an additional stiffener for the package substrate.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: March 27, 2012
    Assignee: Intel Corporation
    Inventors: Prasanna Karpur, Sriram Muthukumar