Abstract: Disclosed herein are devices, apparatus, systems, methods and kits for performing immunoassay tests on a sample. The A sensing apparatus is provided for detecting a plurality of different target analytes in a sample. The apparatus may comprise an array of sensing devices provided on a substrate, each sensing device in the array comprising a working electrode having (1) semiconducting nanostructures disposed thereon and (2) a capture reagent coupled to the semiconducting nanostructures that selectively binds to a different target analyte in the sample. The apparatus may also comprise sensing circuitry that (1) simultaneously detects changes to electron and ion mobility and charge accumulation in the array of sensing devices when the capture reagents in the array of sensing devices selectively bind to the plurality of different target analytes, and (2) determines the presence and concentrations of the plurality of different target analytes in the sample based on the detected changes.

Abstract: Disclosed herein are devices, apparatus, systems, methods and kits for performing immunoassay tests on a sample. The A sensing apparatus is provided for detecting a plurality of different target analytes in a sample. The apparatus may comprise an array of sensing devices provided on a substrate, each sensing device in the array comprising a working electrode having (1) semiconducting nanostructures disposed thereon and (2) a capture reagent coupled to the semiconducting nanostructures that selectively binds to a different target analyte in the sample. The apparatus may also comprise sensing circuitry that (1) simultaneously detects changes to electron and ion mobility and charge accumulation in the array of sensing devices when the capture reagents in the array of sensing devices selectively bind to the plurality of different target analytes, and (2) determines the presence and concentrations of the plurality of different target analytes in the sample based on the detected changes.

Abstract: Electrical characteristics of an electrical signal generated by an affinity-based senor are detected, where the affinity-based sensor is configured to bind to a particular biomarker within a body fluid sample and generate the electrical signal based on binding to the particular biomarker. One or more biometric characteristics of a subject are further detected from one or more other sensors. A data set comprising data describing each of the electrical characteristics and each of the one or more biometric characteristics is provided as an input to a machine learning model, which generates an output based on the input that identifies an amount of the particular biomarker present in the body fluid sample based on the input.

Abstract: A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer.

Abstract: A sensor device includes a porous substrate layer and an array of sensors to accept a sample. The array of sensors includes a plurality of sensors, each of the plurality of sensors includes respective semiconducting nanostructures with a respective capture reagent coupled to the semiconducting nanostructures that selectively binds to a respective target analyte in the sample. The array of sensors includes a first subset of sensors with first capture reagents to bind to biomarkers characteristic of a particular disease and a second subset of sensors with second capture reagents to bind to one of cytokines, chemokines, enzymes, metabolites, or antibodies present in the sample.

Abstract: Systems, methods, and devices include a high-density analog multiplexer topology. Such topologies can be used, for example, in sensor device applications. An analog multiplexer circuit can include circuitry to receive N input signals; and circuitry to generate N selection signals for selecting one of said N data signals to be output from said analog multiplexer circuit. The analog multiplexer comprises one or more analog impedances.

Abstract: Disclosed herein are devices, apparatus, systems, methods and kits for performing immunoassay tests on a sample. The A sensing apparatus is provided for detecting a plurality of different target analytes in a sample. The apparatus may comprise an array of sensing devices provided on a substrate, each sensing device in the array comprising a working electrode having (1) semiconducting nanostructures disposed thereon and (2) a capture reagent coupled to the semiconducting nanostructures that selectively binds to a different target analyte in the sample. The apparatus may also comprise sensing circuitry that (1) simultaneously detects changes to electron and ion mobility and charge accumulation in the array of sensing devices when the capture reagents in the array of sensing devices selectively bind to the plurality of different target analytes, and (2) determines the presence and concentrations of the plurality of different target analytes in the sample based on the detected changes.

Abstract: A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer.

Abstract: A biosensor device includes a porous substrate, where the substrate comprises semiconductor elements functionalized to conjugate with a particular analyte, the semiconductor elements are embedded within at least a portion of the substrate, and the substrate is to absorb fluid capable of carrying the particular analyte. The device further includes two or more electrodes attached to the substrate to correspond to the portion of the substrate, where the portion of the substrate further comprises Room-Temperature Ionic Liquid (RTIL).

Abstract: A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer.

Abstract: A wafer level package device and method are disclosed that include a warpage compensation metal adhered to a backside of a semiconductor wafer for minimizing warpage of the semiconductor wafer, where multiple metal features have been formed on the device side of the semiconductor substrate. The warpage compensation metal may include a copper film.

Abstract: An example biosensor is provided and includes a semiconductor sensing element, a first electrode and a second electrode located on a first plane of the sensing element with a first electric field being applied thereacross, a third electrode located on a second plane of the sensing element parallel to and removed from the first plane with a second electric field being applied across the first electrode and the third electrode perpendicular to the first electric field, and a dielectric substrate having a first portion that constrains a fluid including an analyte on a surface of the sensing element, and a second portion that facilitates dielectric separation of the fluid from the electrodes. The mutually perpendicular electric fields facilitate adjusting a height of a fluid-sensor interface comprising an electrical double layer in the fluid enabling detection and characterization of the analyte.

Abstract: A wafer level package, electronic device including the wafer level package, and fabrication methods are described that include forming a cantilever pillar design as a portion of the wafer level package and/or a segmented solder connection for preventing and reducing connection stress and increasing board level reliability. In implementations, the wafer level device that employs example techniques in accordance with the present disclosure includes at least a section of a processed semiconductor wafer including at least one integrated circuit die, a first dielectric layer disposed on the processed semiconductor wafer, a first pillar, a second pillar formed on the first pillar, a second dielectric layer formed on the first dielectric layer and surrounding a portion of the first pillar and the second pillar, and at least one solder ball disposed on the second pillar.

Abstract: This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.

Abstract: This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.

Abstract: An example biosensor is provided and includes a semiconductor sensing element, a first electrode and a second electrode located on a first plane of the sensing element with a first electric field being applied thereacross, a third electrode located on a second plane of the sensing element parallel to and removed from the first plane with a second electric field being applied across the first electrode and the third electrode perpendicular to the first electric field, and a dielectric substrate having a first portion that constrains a fluid including an analyte on a surface of the sensing element, and a second portion that facilitates dielectric separation of the fluid from the electrodes. The mutually perpendicular electric fields facilitate adjusting a height of a fluid-sensor interface comprising an electrical double layer in the fluid enabling detection and characterization of the analyte.

Abstract: This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.

Abstract: A wafer level package, electronic device including the wafer level package, and fabrication methods are described that include forming a cantilever pillar design as a portion of the wafer level package and/or a segmented solder connection for preventing and reducing connection stress and increasing board level reliability. In implementations, the wafer level device that employs example techniques in accordance with the present disclosure includes at least a section of a processed semiconductor wafer including at least one integrated circuit die, a first dielectric layer disposed on the processed semiconductor wafer, a first pillar, a second pillar formed on the first pillar, a second dielectric layer formed on the first dielectric layer and surrounding a portion of the first pillar and the second pillar, and at least one solder ball disposed on the second pillar.

Abstract: Embodiments of the present invention relate to a method of stiffening a semiconductor coreless package substrate to improve rigidity and resistance against warpage. An embodiment of the method comprises disposing a sacrificial mask on a plurality of contact pads on a second level interconnect (package-to-board interconnect) side of a coreless package substrate, forming a molded stiffener around the sacrificial mask without increasing the effective thickness of the substrate, and removing the sacrificial mask to form a plurality of cavities in the molded stiffener corresponding to the contact pads. Embodiments also include plating the surface of the contact pads and the sidewalls of the cavities in the molded cavities with an electrically conductive material.

Abstract: This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.