Abstract: A delay circuit device configured for delay adjustment monotonicity and method of operating therefor. This delay circuit device is configured with hybrid coarse-fine delay cells and uses a sequence of these delay cells activated in a way that builds-up the delay as a sequence of fine steps until it reaches the coarse delay value. This configuration allows for the continuing build of propagation delay by adding the fine steps of the following delay cells. In this manner, the monotonicity of the signal delay circuit is ensured by the architecture independent from device mismatch, thus eliminating problems with conventional delay circuits such as gaps and overlaps specific the these conventional delay cells.

Abstract: One embodiment relates to a receiver circuit for a data link. The receiver circuit includes at least a first signal path, a second signal path, and a path selector circuit. The first signal path includes first equalization circuitry, and the second signal path includes second equalization circuitry. The path selector circuit is configured to select one signal path of the first and second signal paths. Other embodiments and features are also disclosed.

Abstract: Systems and methods are disclosed for employing an equalization technique that improves equalizer input sensitivity and which reduces power consumption. In particular, an equalization architecture is described that includes a continuous-time linear equalizer and a decision feedback equalizer, each with offset cancellation that enables the equalizer to be used at high data rates. In addition, the equalization structure has a power-saving mode for bypassing the decision feedback equalizer. These offset cancellation and power-saving features are enabled and controlled using programmable logic on a programmable device.

Abstract: Systems and methods for wireless communications are provided. These include data deciphering components, interrupt processing components, adaptive aggregations methods, optimized data path processing, buffer pool processing, application processing where data is formatted in a suitable format for a destination process, and Keystream bank processing among other hardware acceleration features. Such systems and methods are provided to simplify logic designs and mitigate processing steps during wireless network data processing.

Abstract: Aspects disclosed herein address the need in the art for memory management for high speed media access control. A packet buffer may store packets with a first data structure, comprising the packet length, sequence number, and a pointer to a second data structure. Packet data may be stored in a linked list of one or more second data structures. Transmit and receive queues may be formed using linked lists or arrays of the first data structures. Memory locations for storing first and second data structures may be kept in lists indicating free locations for the respective data structure types. A flexible memory architecture is disclosed in which two configurations may be selected. Various other aspects are also presented.

Abstract: Systems and methods are disclosed for employing an equalization technique that improves equalizer input sensitivity and which reduces power consumption. In particular, an equalization architecture is described that includes a continuous-time linear equalizer and a decision feedback equalizer, each with offset cancellation that enables the equalizer to be used at high data rates. In addition, the equalization structure has a power-saving mode for bypassing the decision feedback equalizer. These offset cancellation and power-saving features are enabled and controlled using programmable logic on a programmable device.

Abstract: One embodiment relates to a receiver circuit for a data link. The receiver circuit includes at least a first signal path, a second signal path, and a path selector circuit. The first signal path includes first equalization circuitry, and the second signal path includes second equalization circuitry. The path selector circuit is configured to select one signal path of the first and second signal paths. Other embodiments and features are also disclosed.

Abstract: Equalizer circuitry on an integrated circuit (“IC”) includes first, second, and third continuous time, equalizer stages connected in series. Each stage includes peaking inductor circuitry. The equalizer circuitry may further include controllably variable, static, DC mode offset voltage compensation circuitry and/or dynamic, continuous mode, offset voltage compensation circuitry for respectively reducing DC voltage offset and/or time-varying, continuous mode voltage offset between an output of the third equalizer stage and utilization circuitry to which that output is applied. The first equalizer stage may be preceded by termination circuitry having controllably variable impedance. Differential circuitry and signalling may be used for various circuit components. The equalizer circuitry is particularly useful for fabrication as part of a programmable IC, using 28 nm CMOS technology, and as a receiver equalizer for a high-speed serial data signal having a bit rate of 20-25 Gbps.

Abstract: Aspects disclosed herein address the need in the art for memory management for high speed media access control. A packet buffer may store packets with a first data structure, comprising the packet length, sequence number, and a pointer to a second data structure. Packet data may be stored in a linked list of one or more second data structures. Transmit and receive queues may be formed using linked lists or arrays of the first data structures. Memory locations for storing first and second data structures may be kept in lists indicating free locations for the respective data structure types. A flexible memory architecture is disclosed in which two configurations may be selected. Various other aspects are also presented.

Abstract: One embodiment relates to an integrated circuit including a first strip of phase-locked loop (PLL) circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. The PLL circuits in the first and second strips may be configured by programming the integrated circuit. Another embodiment relates to an integrated circuit including a plurality of phase-locked loop (PLL) circuits and a plurality of physical media attachment (PMA) triplet modules adjacent to the plurality of PLL circuits. Each PMA triplet module includes first, second and third channels. The first and third channels are arranged for use as receiving channels, and the second channel is arranged to be configurable as either a receiving channel or a clock multiplication unit. Other embodiments and features are also disclosed.

Abstract: A test driver transmitter drives a test signal through a resistive termination circuit to a first pin to test components on a board during a boundary scan test operation. A test receiver receives the test signal through a second pin and a pass gate coupled to the second pin during the boundary scan test operation. A test signal is transmitted to the test receiver during loopback operation through a loopback circuit.

Abstract: A circuit includes a current mirror circuit and first and second transistors coupled as a differential pair. A first input voltage is provided to a control input of the first transistor. A second input voltage is provided to a control input of the second transistor. The current mirror circuit includes a third transistor, a fourth transistor coupled to the third transistor, and a fifth transistor coupled in series with the fourth transistor. The third transistor provides a current through the differential pair that is proportional to a current through the fourth transistor. A control input of the fourth transistor is coupled between the fifth transistor and a source of current.

Abstract: One embodiment relates to a continuous-time circuit configured with an offset cancellation loop. The continuous-time circuit includes a multi-stage amplifier chain, including a first amplifier stage and a last amplifier stage, and an offset cancellation loop. The offset cancellation loop is configured to receive an output of the last amplifier stage and to provide an offset correction voltage signal to the first amplifier stage. The offset compensation loop may create one dominant pole and a single consequential parasitic pole so as to have greater stability and may advantageously achieve a second-order roll-off in response magnitude at higher frequencies. Other embodiments, aspects, and features are also disclosed.

Abstract: One embodiment relates to a continuous-time circuit configured with an offset cancellation loop. The continuous-time circuit includes a multi-stage amplifier chain, including a first amplifier stage and a last amplifier stage, and an offset cancellation loop. The offset cancellation loop is configured to receive an output of the last amplifier stage and to provide an offset correction voltage signal to the first amplifier stage. The offset compensation loop may create one dominant pole and a single consequential parasitic pole so as to have greater stability and may advantageously achieve a second-order roll-off in response magnitude at higher frequencies. Other embodiments, aspects, and features are also disclosed.

Abstract: An integrated circuit (“IC”) may include circuitry for use in testing a serial data signal. The IC may include circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. The IC may also include circuitry for receiving the serial data signal and performing a bit error rate (“BER”) analysis in such a signal. The IC may provide output signals indicative of results of its operations. The IC can operate in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.

Abstract: Aspects disclosed herein address the need in the art for memory management for high speed media access control. A packet buffer may store packets with a first data structure, comprising the packet length, sequence number, and a pointer to a second data structure. Packet data may be stored in a linked list of one or more second data structures. Transmit and receive queues may be formed using linked lists or arrays of the first data structures. Memory locations for storing first and second data structures may be kept in lists indicating free locations for the respective data structure types. A flexible memory architecture is disclosed in which two configurations may be selected. In a first configuration, a first memory comprises per-flow parameters for multiple flows, and a second memory comprises a packet buffer. In a second configuration, the first memory comprises per-flow pointers to per-flow parameters in the second memory. The packet buffer resides in a third memory.

Abstract: A power-efficient wireless device is equipped with multiple (N) antennas. Each antenna is associated with a transmitter unit and a receiver unit. The wireless device also has processing units used to perform various digital processing tasks. The transmitter units, receiver units, and processing units may be selectively enabled or disabled. In an idle state, the wireless device may enable only a subset (e.g., one) of the N receiver units and one or few processing units for signal detection and acquisition. For active communication, the wireless device may enable Ntx transmitter units for data transmission and/or Nrx receiver units for data reception, where 1?Ntx?N and 1?Nrx?N. The enabled processing units may also be clocked at a lower frequency whenever data is transmitted or received at a data rate lower than the highest data rate. The wireless device may go to sleep whenever possible to conserve power.

Abstract: A test driver transmitter drives a test signal through a resistive termination circuit to a first pin to test components on a board during a boundary scan test operation. A test receiver receives the test signal through a second pin and a pass gate coupled to the second pin during the boundary scan test operation. A test signal is transmitted to the test receiver during loopback operation through a loopback circuit.

Abstract: Systems and methods for wireless communications are provided. These include data deciphering components, interrupt processing components, adaptive aggregations methods, optimized data path processing, buffer pool processing, application processing where data is formatted in a suitable format for a destination process, and Keystream bank processing among other hardware acceleration features. Such systems and methods are provided to simplify logic designs and mitigate processing steps during wireless network data processing.

Abstract: Aspects disclosed herein address the need in the art for memory management for high speed media access control. A packet buffer may store packets with a first data structure, comprising the packet length, sequence number, and a pointer to a second data structure. Packet data may be stored in a linked list of one or more second data structures. Transmit and receive queues may be formed using linked lists or arrays of the first data structures. Memory locations for storing first and second data structures may be kept in lists indicating free locations for the respective data structure types. A flexible memory architecture is disclosed in which two configurations may be selected. In a first configuration, a first memory comprises per-flow parameters for multiple flows, and a second memory comprises a packet buffer. In a second configuration, the first memory comprises per-flow pointers to per-flow parameters in the second memory. The packet buffer resides in a third memory.