Abstract: The present invention discloses an OLED display having a first row of light emitting diodes and a second row of light emitting diodes. A first sensor circuit is coupled to a light emitting diode of the first linear array for detecting an output of the light emitting diode of the first linear array. A second sensor circuit is coupled to a light emitting diode of the second linear array for detecting an output of the light emitting diode of the second linear array. A control circuit simultaneously causes the light emitting diode of the first linear array to emit light and the sensor circuit coupled to the light emitting diode of the second linear array to provide information corresponding to the detected output of the light emitting diode of the second linear array to a sensor reader circuit.

Abstract: A controller chip has programmable registers that control the operation of the controller chip. The controller chip connects to a microprocessor and bus controller through a bus that performs burst cycles. Although only one address (the starting address) is sent over the bus during the burst cycle, multiple data words are sent in the burst. These data words are written to addresses that follow the starting address in a fixed burst sequence. Programmable registers are accessed in an order that is not the fixed burst sequence. The programmable registers are accessed in a non-sequential order in a single burst cycle by using a mapping control word. The starting address is is set to the address of a mapping control register in the controller chip. The mapping control word is sent as the first data word after the starting address. The mapping control word is decoded to determine which of the programmable registers are to be written during the burst cycle.

Abstract: A display system in a computer or multimedia system maintains a predetermined image quality. The display system includes an intelligent display driver controller (IDDC), a serial PROM, display screen, and sensors. The IDDC controls display of input image data on the display screen based on a control set. The serial PROM stores a plurality of such control sets, each of which has a predetermined effect on the image quality. The sensor measures a parameter, a change in which may degrade the image quality on the display screen. In response to such a change, the IDDC retrieves a new control set from the serial PROM, and controls display of input image data based on the new control set retrieved. As a result, the IDDC maintains the predetermined image quality on the display system independent of change in the measured parameter.

Abstract: A digital system provides command data to a display system during the display time period such that minimal image degradation occurs. The digital system includes a CPU coupled to a graphics controller coupled to a display system via a cable. The display system includes an intelligent display driver controller (IDDC), driver circuits, display screen, and possibly sensors. The IDDC operates on image data and instructs the driver circuits to display an image on the display screen. Operating condition changes measured by transducers may result in a degradation in image quality unless a response is made. The digital system may automatically respond to operating condition changes to maintain a predetermined image quality level. Alternatively a user's request may change the image quality. In either case the CPU is interrupted and it provides one or more control sets of command data interspersed within the image data transparently to the graphics controller.

Abstract: A method and apparatus for monitoring and controlling power to a device such as a PCMCIA/PC card. A PCMCIA/PC card adapter is provided for communicating data and control signals to and from a PCMCIA/PC card and a host processor. The PCMCIA/PC card adapter may communicate with the PCMCIA/PC card to determine the correct voltage(s) for the PCMCIA/PC card. The PCMCIA/PC card may then communicate instruct a power control circuit to provide an appropriate voltage to the PCMCIA/PC card. The power control circuit may be provided with status monitoring registers containing status data reflecting monitored conditions of the PCMCIA/PC card and power supply. A System Management Bus (SMB) may link the power control circuit and the PCMCIA/PC card adapter. If an abnormal status is detected in the PCMCIA/PC card or power supply (e.g.

Abstract: A peripheral device capable of generating interrupt request signals compliant with the Industry Standard Architecture (ISA) protocol, and the Peripheral Component Interconnect (PCI) protocol. The peripheral device comprises a signal generator block which selectively generates either the interrupt request signals of the PCI protocol or a set of bits representative of interrupt request signals of the ISA protocol. The set of bits are transferred serially to a converter circuit which generates the interrupt request signals of the ISA protocol based on the bits. The signal generator block generates bits in such a way as to support both pulse mode and level mode interrupt request signals for the ISA protocol.