Patents by Inventor Sriram Sambamurthy
Sriram Sambamurthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113914Abstract: An apparatus and method for efficiently performing power management for multiple clients of a semiconductor chip that supports remote manageability. In various implementations, a network interface receives a packet, and sends at least an indication of the packet to a manageability processing circuitry (MPC) of a processing node with multiple clients for processing tasks. The MPC determines whether a client or itself is a destination needed to process the packet. If the destination is the MPC, then packet processing is done by the MPC without involvement from the clients, which can be in an idle state. For example, the MPC can process a remote manageability packet requesting diagnostic information from one or more clients of the processing node. The network interface and the MPC use a sideband communication channel for data transmission, which foregoes lane training for further reduction in latency and power consumption.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Inventors: Sriram Sambamurthy, Indrani Paul, David Boardman Kramer, Madhusudan Chilakam
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Publication number: 20240085964Abstract: A system and method for updating power supply voltages due to variations from aging are described. A functional unit includes a power supply monitor capable of measuring power supply variations in a region of the functional unit. An age counter measures an age of the functional unit. A control unit notifies the power supply monitor to measure an operating voltage reference. When the control unit receives a measured operating voltage reference, the control unit determines an updated age of the region different from the current age based on the measured operating voltage reference. The control unit updates the age counter with the corresponding age, which is younger than the previous age in some cases due to the region not experiencing predicted stress and aging. The control unit is capable of determining a voltage adjustment for the operating voltage reference based on an age indicated by the age counter.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Inventors: Sriram Sambamurthy, Sriram Sundaram, Indrani Paul, Larry David Hewitt, Anil Harwani, Aaron Joseph Grenat, Dana Glenn Lewis, Leonardo Piga, Wonje Choi, Karthik Rao
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Patent number: 11886224Abstract: A processing unit of a processing system compiles a priority queue listing of a plurality of processor cores to run a workload based on a cost of running the workload on each of the processor cores. The cost is based on at least one of a system usage policy, characteristics of the workload, and one or more physical constraints of each processor core. The processing unit selects a processor core based on the cost to run the workload and communicates an identifier of the selected processor core to an operating system of the processing system.Type: GrantFiled: July 31, 2020Date of Patent: January 30, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Leonardo De Paula Rosa Piga, Karthik Rao, Indrani Paul, Mahesh Subramony, Kenneth Mitchell, Dana Glenn Lewis, Sriram Sambamurthy, Wonje Choi
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Patent number: 11829222Abstract: A system and method for updating power supply voltages due to variations from aging are described. A functional unit includes a power supply monitor capable of measuring power supply variations in a region of the functional unit. An age counter measures an age of the functional unit. A control unit notifies the power supply monitor to measure an operating voltage reference. When the control unit receives a measured operating voltage reference, the control unit determines an updated age of the region different from the current age based on the measured operating voltage reference. The control unit updates the age counter with the corresponding age, which is younger than the previous age in some cases due to the region not experiencing predicted stress and aging. The control unit is capable of determining a voltage adjustment for the operating voltage reference based on an age indicated by the age counter.Type: GrantFiled: December 18, 2020Date of Patent: November 28, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Sriram Sambamurthy, Sriram Sundaram, Indrani Paul, Larry David Hewitt, Anil Harwani, Aaron Joseph Grenat, Dana Glenn Lewis, Leonardo Piga, Wonje Choi, Karthik Rao
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Publication number: 20230350480Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.Type: ApplicationFiled: June 23, 2023Publication date: November 2, 2023Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Indrani Paul, Sriram Sambamurthy, Larry David Hewitt, Kevin M. Lepak, Samuel D. Naffziger, Adam Neil Calder Clark, Aaron Joseph Grenat, Steven Frederick Liepe, Sandhya Shyamasundar, Wonje Choi, Dana Glenn Lewis, Leonardo de Paula Rosa Piga
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Patent number: 11714442Abstract: An electronic device includes an accelerated processing unit (APU) and multiple elements. The APU performs operations for a platform boost and throttle (PBT) controller. For the operations, the APU receives a platform electrical power limit, the platform electrical power limit being a limit on a total electrical power allowed to be consumed by a group of the elements at a given time. The APU then determines a present platform electrical power consumption. The APU next adjusts one or more operating parameters for specified elements from among the group of elements to control electrical power consumption by the specified elements based on a relationship between the present platform electrical power consumption and the platform electrical power limit.Type: GrantFiled: December 23, 2021Date of Patent: August 1, 2023Assignees: ATI Technologies ULC, Advanced Micro Devices Inc.Inventors: Meeta Surendramohan Srivastav, Ashwini Chandrashekhara Holla, Alex Sabino Duenas, Xinzhe Li, Michael John Austin, Indrani Paul, Sriram Sambamurthy
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Patent number: 11703930Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.Type: GrantFiled: July 21, 2021Date of Patent: July 18, 2023Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Indrani Paul, Sriram Sambamurthy, Larry David Hewitt, Kevin M. Lepak, Samuel D. Naffziger, Adam Neil Calder Clark, Aaron Joseph Grenat, Steven Frederick Liepe, Sandhya Shyamasundar, Wonje Choi, Dana Glenn Lewis, Leonardo de Paula Rosa Piga
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Publication number: 20230205248Abstract: An electronic device includes an accelerated processing unit (APU) and multiple elements. The APU performs operations for a platform boost and throttle (PBT) controller. For the operations, the APU receives a platform electrical power limit, the platform electrical power limit being a limit on a total electrical power allowed to be consumed by a group of the elements at a given time. The APU then determines a present platform electrical power consumption. The APU next adjusts one or more operating parameters for specified elements from among the group of elements to control electrical power consumption by the specified elements based on a relationship between the present platform electrical power consumption and the platform electrical power limit.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Inventors: Meeta Surendramohan Srivastav, Ashwini Chandrashekhara Holla, Alex Sabino Duenas, Xinzhe Li, Michael John Austin, Indrani Paul, Sriram Sambamurthy
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Publication number: 20230088994Abstract: An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.Type: ApplicationFiled: November 23, 2022Publication date: March 23, 2023Inventors: Karthik RAO, Indrani Paul, Donny YI, Oleksandr KHODORKOVSKY, Leonardo DE PAULA ROSA PIGA, Wonje CHOI, Dana G. LEWIS, Sriram SAMBAMURTHY
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Patent number: 11543877Abstract: An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.Type: GrantFiled: March 31, 2021Date of Patent: January 3, 2023Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULCInventors: Karthik Rao, Indrani Paul, Donny Yi, Oleksandr Khodorkovsky, Leonardo De Paula Rosa Piga, Wonje Choi, Dana G. Lewis, Sriram Sambamurthy
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Publication number: 20220317757Abstract: An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Inventors: Karthik RAO, Indrani PAUL, Donny YI, Oleksandr KHODORKOVSKY, Leonardo DE PAULA ROSA PIGA, Wonje CHOI, Dana G. LEWIS, Sriram SAMBAMURTHY
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Publication number: 20220100249Abstract: A system and method for updating power supply voltages due to variations from aging are described. A functional unit includes a power supply monitor capable of measuring power supply variations in a region of the functional unit. An age counter measures an age of the functional unit. A control unit notifies the power supply monitor to measure an operating voltage reference. When the control unit receives a measured operating voltage reference, the control unit determines an updated age of the region different from the current age based on the measured operating voltage reference. The control unit updates the age counter with the corresponding age, which is younger than the previous age in some cases due to the region not experiencing predicted stress and aging. The control unit is capable of determining a voltage adjustment for the operating voltage reference based on an age indicated by the age counter.Type: ApplicationFiled: December 18, 2020Publication date: March 31, 2022Inventors: Sriram Sambamurthy, Sriram Sundaram, Indrani Paul, Larry David Hewitt, Anil Harwani, Aaron Joseph Grenat, Dana Glenn Lewis, Leonardo Piga, Wonje Choi, Karthik Rao
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Publication number: 20210406092Abstract: A processing unit of a processing system compiles a priority queue listing of a plurality of processor cores to run a workload based on a cost of running the workload on each of the processor cores. The cost is based on at least one of a system usage policy, characteristics of the workload, and one or more physical constraints of each processor core. The processing unit selects a processor core based on the cost to run the workload and communicates an identifier of the selected processor core to an operating system of the processing system.Type: ApplicationFiled: July 31, 2020Publication date: December 30, 2021Inventors: Leonardo DE PAULA ROSA PIGA, Karthik RAO, Indrani PAUL, Mahesh SUBRAMONY, Kenneth MITCHELL, Dana Glenn LEWIS, Sriram SAMBAMURTHY, Wonje CHOI
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Publication number: 20210349517Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.Type: ApplicationFiled: July 21, 2021Publication date: November 11, 2021Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Indrani Paul, Sriram Sambamurthy, Larry David Hewitt, Kevin M. Lepak, Samuel D. Naffziger, Adam Neil Calder Clark, Aaron Joseph Grenat, Steven Frederick Liepe, Sandhya Shyamasundar, Wonje Choi, Dana Glenn Lewis, Leonardo de Paula Rosa Piga
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Patent number: 11073888Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.Type: GrantFiled: May 31, 2019Date of Patent: July 27, 2021Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Indrani Paul, Sriram Sambamurthy, Larry David Hewitt, Kevin M. Lepak, Samuel D. Naffziger, Adam Neil Calder Clark, Aaron Joseph Grenat, Steven Frederick Liepe, Sandhya Shyamasundar, Wonje Choi, Dana Glenn Lewis, Leonardo de Paula Rosa Piga
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Publication number: 20200379544Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.Type: ApplicationFiled: May 31, 2019Publication date: December 3, 2020Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Indrani Paul, Sriram Sambamurthy, Larry David Hewitt, Kevin M. Lepak, Samuel D. Naffziger, Adam Neil Calder Clark, Aaron Joseph Grenat, Steven Frederick Liepe, Sandhya Shyamasundar, Wonje Choi, Dana Glenn Lewis, Leonardo de Paula Rosa Piga
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Patent number: 10060955Abstract: A processing system includes one or more power supply monitors (PSMs) to measure one or more first voltages corresponding to one or more locations in the processing system. The measurements are performed concurrently with the processing system executing one or more code loops. The processing system also includes calibration logic to modify a second voltage provided to the processing system based on a comparison of a reference voltage and the one or more first voltages. The reference voltage is determined based on previous execution of the one or more code loops by the processing system.Type: GrantFiled: June 25, 2014Date of Patent: August 28, 2018Assignee: Advanced Micro Devices, Inc.Inventors: Aaron J. Grenat, Robert A. Hershberger, Sriram Sambamurthy, Samuel D. Naffziger, Christopher E. Tressler, Sho-Chien Kang, Joseph P. Shannon, Krishna Sai Bernucho, Ashwin Chincholi, Michael J. Austin, Steven F. Liepe, Umair B. Cheema
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Patent number: 9372499Abstract: A clock doubler includes a first NAND gate having a first input for receiving a clock input signal and a second input, a second NAND gate having a first input and a second input for receiving a complement of the clock input signal, an output NAND gate having a first and second inputs coupled to outputs of the first and second NAND gates, respectively, and an output for providing a clock output signal, an inverter chain having an input for receiving the clock input signal and responsive to first and second control signals to selectively provide a first true output to the first input of the second NAND gate, and a second complementary output to the second input of the first NAND gate, and a control signal generation circuit providing the first and second control signals in response to the outputs of the first and second NAND gates.Type: GrantFiled: January 21, 2014Date of Patent: June 21, 2016Inventors: Sriram Sambamurthy, Arun Sundaresan Iyer, Alok Baluni, Aaron Grenat
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Patent number: 9319037Abstract: In one form, a clock doubler includes a switched inverter, an exclusive logic circuit, and a control signal generation circuit. The switched inverter has first and second control inputs for respectively receiving first and second control signals, a signal input for receiving a clock input signal, and an output. The exclusive logic circuit has a first input for receiving the clock input signal, a second input coupled to the output of the switched inverter, and an output for providing a clock output signal. A control signal generation circuit provides the first and second control signals in response to the clock output signal. The clock doubler may be used in a clock distribution circuit for an integrated circuit that also includes a phase locked loop for providing the input clock signals, and a plurality of clock sub-domains each having one of the clock doublers.Type: GrantFiled: February 3, 2014Date of Patent: April 19, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Arun Sundaresan Iyer, Alok Baluni, Samuel Naffziger, Sriram Sambamurthy
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Publication number: 20150378411Abstract: A processing system includes one or more power supply monitors (PSMs) to measure one or more first voltages corresponding to one or more locations in the processing system. The measurements are performed concurrently with the processing system executing one or more code loops. The processing system also includes calibration logic to modify a second voltage provided to the processing system based on a comparison of a reference voltage and the one or more first voltages. The reference voltage is determined based on previous execution of the one or more code loops by the processing system.Type: ApplicationFiled: June 25, 2014Publication date: December 31, 2015Inventors: Aaron J. Grenat, Robert A. Hershberger, Sriram Sambamurthy, Samuel D. Naffziger, Christopher E. Tressler, Sho-Chien Kang, Joseph P. Shannon, Krishna Sai Bernucho, Ashwin Chincholi, Michael J. Austin, Steven F. Liepe, Umair B. Cheema