Patents by Inventor Sriram Sankaranarayanan

Sriram Sankaranarayanan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230325613
    Abstract: A smart translation system that translates the input content received from an application based on translation metadata and the application is disclosed. It is initially determined if a translation of the input content exists in a user cache. If it is determined that the translation of the input content exists in the user cache, the translation is retrieved from the user cache. Else, if it is determined that the translation of the input content does not exist in the user cache, the domain and language contexts of the input content are determined and an automatic translation engine is selected based on the contexts and the translation metadata. The translated content is presented to the user via the application while maintaining the look and feel of the application.
    Type: Application
    Filed: August 31, 2022
    Publication date: October 12, 2023
    Applicant: ACCENTURE GLOBAL SOLUTIONS LIMITED
    Inventors: Prakash GHATAGE, Naveen Kumar THANGARAJ, Kaustubh KURHEKAR, Sreevidya PRASAD, Sriram SANKARANARAYANAN
  • Patent number: 8924938
    Abstract: A system and method for analyzing a computer program includes performing a static analysis on a program to determine property correctness. Test cases are generated and conducted to provide test output data. Hypotheses about aspects of execution of the program are produced to classify paths for test cases to determine whether the test cases have been encountered or otherwise. In accordance with the hypothesis, new test cases are generated to cause the program to exercise behavior which is outside of the encountered test cases.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: December 30, 2014
    Assignee: NEC Laboratories America, Inc.
    Inventors: Richard Chang, Sriram Sankaranarayanan, Guofei Jiang, Franjo Ivancic
  • Patent number: 8719793
    Abstract: A scalable, computer implemented method for finding subtle flaws in software programs. The method advantageously employs 1) scope bounding which limits the size of a generated model by excluding deeply-nested function calls, where the scope bounding vector is chosen non-monotonically, and 2) automatic specification inference which generates constraints for functions through the effect of a light-weight and scalable global analysis. Advantageously, scalable software model checking is achieved while at the same time finding more bugs.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: May 6, 2014
    Assignees: NEC Laboratories America, Inc., NEC Corporation
    Inventors: Naoto Maeda, Franjo Ivancic, Sriram Sankaranarayanan, Aarti Gupta
  • Patent number: 8601459
    Abstract: A system and method for discovering a set of possible iteration sequences for a given loop in a software program is described, to transform the loop representation. In a program containing a loop, the loop is partitioned into a plurality of portions based on splitting criteria. Labels are associated with the portions, and an initial loop automaton is constructed that represents the loop iterations as a regular language over the labels corresponding to the portions in the program. Subsequences of the labels are analyzed to determine infeasibility of the subsequences permitted in the automaton. The automaton is refined by removing all infeasible subsequences to discover a set of possible iteration sequences in the loop. The resulting loop automaton is used in a subsequent program verification or analysis technique to find violations of correctness properties in programs.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: December 3, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventors: Sriram Sankaranarayanan, Aarti Gupta, Gogul Balakrishnan
  • Patent number: 8539451
    Abstract: Methods and systems for verifying the precision of a program that utilizes floating point operations are disclosed. Interval and affine arithmetic can be employed to build a model of the program including floating point operations and variables that are expressed as reals and integers, thereby permitting accurate determination of precision loss using a model checker. Abstract interpretation can be also employed to simplify the model. In addition, counterexample-guided abstraction refinement can be used to refine the values of parametric error constants introduced in the model.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: September 17, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventors: Franjo Ivancic, Malay K. Ganai, Sriram Sankaranarayanan, Aarti Gupta
  • Patent number: 8522226
    Abstract: A system and method for discovering a set of possible iteration sequences for a given loop in a software program is described, to transform the loop representation. In a program containing a loop, the loop is partitioned into a plurality of portions based on splitting criteria. Labels are associated with the portions, and an initial loop automaton is constructed that represents the loop iterations as a regular language over the labels corresponding to the portions in the program. Subsequences of the labels are analyzed to determine infeasibility of the subsequences permitted in the automaton. The automaton is refined by removing all infeasible subsequences to discover a set of possible iteration sequences in the loop. The resulting loop automaton is used in a subsequent program verification or analysis technique to find violations of correctness properties in programs.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: August 27, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventors: Sriram Sankaranarayanan, Aarti Gupta, Gogul Balakrishnan
  • Patent number: 8402440
    Abstract: Systems and methods are disclosed to verify a program by symbolically enumerating path programs; verifying each path program to determine if the path program is correct or leads to a violation of a correctness property; determining a conflict set from the path program if the path program is proved correct; using the conflict set to avoid enumerating other related path programs that are also correct.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: March 19, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventors: Sriram Sankaranarayanan, Franjo Ivancic, William R Harris, Aarti Gupta, Gogul Balakrishnan
  • Patent number: 8374840
    Abstract: A system and method for generating test vectors includes generating traces of a system model or program stored in memory using a simulation engine. Simulated inputs are globally optimized using a fitness objective computed using a computer processing device. The simulation inputs are adjusted in accordance with feedback from the traces and fitness objective values by computing a distance between the fitness objective value and a reachability objective. Test input vectors are output based upon optimized fitness objective values associated with the simulated inputs to test the system model or program stored in memory.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: February 12, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventors: Sriram Sankaranarayanan, Franjo Ivancic, Aarti Gupta, Truong X. Nghiem
  • Patent number: 8365152
    Abstract: A system and method for infeasible path detection includes performing a static analysis on a program to prove a property of the program. If the property is not proved, infeasible paths in the program are determined by performing a path-insensitive abstract interpretation. Information about such infeasible paths is used to achieve the effects of path-sensitivity in path-insensitive program analysis.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: January 29, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventors: Gogul Balakrishnan, Sriram Sankaranarayanan, Franjo Ivancic, Aarti Gupta
  • Patent number: 8352222
    Abstract: In accordance with aspects of the present principles, an over-approximation of reachable states of a hybrid system may be determined by utilizing template polyhedra. Policy iteration may be utilized to obtain an over-approximation of reachable states in the form of a relaxed invariant based upon template polyhedra expressions. The relaxed invariant may be used to construct a flowpipe to refine the over-approximation and thereby determine the reachable states of the hybrid system.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: January 8, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventors: Sriram Sankaranarayanan, Franjo Ivancic
  • Publication number: 20120151449
    Abstract: A scalable, computer implemented method for finding subtle flaws in software programs. The method advantageously employs 1) scope bounding which limits the size of a generated model by excluding deeply-nested function calls, where the scope bounding vector is chosen non-monotonically, and 2) automatic specification inference which generates constraints for functions through the effect of a light-weight and scalable global analysis. Advantageously, scalable software model checking is achieved while at the same time finding more bugs.
    Type: Application
    Filed: December 8, 2011
    Publication date: June 14, 2012
    Applicant: NEC LABORATORIES AMERICA, INC.
    Inventors: Naoto Maeda, Franjo Ivancic, Sriram Sankaranarayanan, Aarti Gupta
  • Patent number: 8191045
    Abstract: A system and method for mining program specifications includes generating unit tests to exercise functions of a library through an application program interface (API), based upon an (API) signature. A response to the unit tests is determined to generate a transaction in accordance with a target behavior. The transaction is converted into a relational form, and specifications of the library are learned using an inductive logic programming tool from the relational form of the transaction.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: May 29, 2012
    Assignee: NEC Laboratories America, Inc.
    Inventors: Sriram Sankaranarayanan, Franjo Ivancic, Aarti Gupta
  • Patent number: 8185875
    Abstract: A system and method for race warning generation for computer program verification includes determining shared variables and determining context-sensitive points-to sets for lock pointers by focusing on pointers that may affect aliases of lock pointers, and by leveraging function summarization. Locksets are determined at locations where shared variables are accessed using the points-to sets for lock pointers. Warnings are based on disjointness of locksets.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: May 22, 2012
    Assignee: NEC Laboratories America, Inc.
    Inventors: Vineet Kahlon, Yu Yang, Sriram Sankaranarayanan, Aarti Gupta
  • Patent number: 8126831
    Abstract: A system and method for inferring preconditions for procedures in a program includes formulating predicates based on inputs to a procedure, including formal arguments, global variables and external environment. Truth assignments are sampled to the predicates to provide truth assignments that lead to a feasible set of input values. Test cases are generated for testing the program in accordance with the truth assignments having feasible sets of input values. The truth assignments are classified to the predicates as providing an error or not providing an error.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: February 28, 2012
    Assignee: NEC Laboratories America, Inc.
    Inventors: Sriram Sankaranarayanan, Franjo Ivancic, Aarti Gupta
  • Patent number: 8006239
    Abstract: A computer implemented method for generating a representation of relationships between variables in a program employing Symbolic Range Constraints (SRCs) wherein the SRCs are of the form ?:^i=1nli?xi?ui where for each i ?[l,n], the linear expressions li,ui are made up of variables in the set{xi+1, . . . ,xn} and wherein the SRCs comprise linear, convex, and triangulated constraints for a given variable order.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: August 23, 2011
    Assignee: NEC Laboratories America, Inc.
    Inventors: Sriram Sankaranarayanan, Aarti Gupta, Franjo Ivancic, Ilya Shlyakhter
  • Publication number: 20100299651
    Abstract: A system and method for testing robustness of a simulation model of a cyber-physical system includes computing a set of symbolic simulation traces for a simulation model for a continuous time system stored in memory, based on a discrete time simulation of given test inputs stored in memory. Simulation errors are accounted for due to at least one of numerical instabilities and numeric computations. The set of symbolic simulation traces are validated with respect to validation properties in the simulation model. Portions of the simulation model description are identified that are sources of the simulation errors.
    Type: Application
    Filed: February 19, 2010
    Publication date: November 25, 2010
    Applicant: NEC Laboratories America, Inc.
    Inventors: GEORGIOS FAINEKOS, Sriram Sankaranarayanan, Franjo Ivancic, Aarti Gupta
  • Publication number: 20100293530
    Abstract: Methods and systems for verifying the precision of a program that utilizes floating point operations are disclosed. Interval and affine arithmetic can be employed to build a model of the program including floating point operations and variables that are expressed as reals and integers, thereby permitting accurate determination of precision loss using a model checker. Abstract interpretation can be also employed to simplify the model. In addition, counterexample-guided abstraction refinement can be used to refine the values of parametric error constants introduced in the model.
    Type: Application
    Filed: April 16, 2010
    Publication date: November 18, 2010
    Applicant: NEC Laboratories America, Inc.
    Inventors: FRANJO IVANCIC, Malay K. Ganai, Sriram Sankaranarayanan, Aarti Gupta
  • Publication number: 20100205592
    Abstract: A system and method for discovering a set of possible iteration sequences for a given loop in a software program is described, to transform the loop representation. In a program containing a loop, the loop is partitioned into a plurality of portions based on splitting criteria. Labels are associated with the portions, and an initial loop automaton is constructed that represents the loop iterations as a regular language over the labels corresponding to the portions in the program. Subsequences of the labels are analyzed to determine infeasibility of the subsequences permitted in the automaton. The automaton is refined by removing all infeasible subsequences to discover a set of possible iteration sequences in the loop. The resulting loop automaton is used in a subsequent program verification or analysis technique to find violations of correctness properties in programs.
    Type: Application
    Filed: February 8, 2010
    Publication date: August 12, 2010
    Applicant: NEC Laboratories America, Inc.
    Inventors: SRIRAM SANKARANARAYANAN, Aarti Gupta, Gogul Balakrishnan
  • Publication number: 20100094611
    Abstract: A system and method for generating test vectors includes generating traces of a system model or program stored in memory using a simulation engine. Simulated inputs are globally optimized using a fitness objective computed using a computer processing device. The simulation inputs are adjusted in accordance with feedback from the traces and fitness objective values by computing a distance between the fitness objective value and a reachability objective. Test input vectors are output based upon optimized fitness objective values associated with the simulated inputs to test the system model or program stored in memory.
    Type: Application
    Filed: October 14, 2009
    Publication date: April 15, 2010
    Applicant: NEC Laboratories America, Inc.
    Inventors: Sriram Sankaranarayanan, Franjo Ivancic, Aarti Gupta, Truong Nghiem
  • Publication number: 20100058475
    Abstract: Embodiments of the present invention combine static analysis, source code instrumentation and feedback-guided fuzz testing to automatically detect resource exhaustion denial of service attacks in software and generate inputs of coma for vulnerable code segments. The static analysis of the code highlights portions that are potentially vulnerable, such as loops and recursions whose exit conditions are dependent on user input. The code segments are dynamically instrumented to provide a feedback value at the end of each execution. Evolutionary techniques are then employed to search among the possible inputs to find inputs that maximize the feedback score.
    Type: Application
    Filed: March 3, 2009
    Publication date: March 4, 2010
    Applicant: NEC Laboratories America, Inc.
    Inventors: Suresh Thummalapenta, Guofei Jiang, Sriram Sankaranarayanan, Franjo Ivancic