Abstract: Procedures are disclosed to automate constraint and power mode (PM) setup determination for quiescent power supply current (IDDQ) testing of a semiconductor design. Starting with known constraints and PM setup, if available, an estimation is run to obtain minimum, lower bound (LB), expected, upper bound (UB), and maximum IDDQ estimates for individual cells. The estimates are sorted by range (UB-LB), and by elevation (expected-minimum). A constraint is added to control the power of the cell with the highest range. A constraint or a PM entry is added to reduce elevation of the cell with the highest elevation, based on a predetermined property of the cell. With the adjusted constraints and PM setup, the steps are repeated. Iteration continues until (1) the top cells are not custom cells, memories, or macros, or (2) the contributions of the top cells to the design's range and elevation are below predetermined limits.

Abstract: A technique for improving multiple critical timing paths that exhibit similar characteristics has been discovered. The technique efficiently improves multiple critical timing paths by reducing the number of unique critical timing path patterns for analysis. In some embodiments of the present invention a method for use in connection with an integrated circuit design includes identifying distinct timing paths of the integrated circuit design. The distinct timing paths have timing violations. The method includes associating a first plurality of the distinct timing paths with a first set of timing paths. Individual ones of the first plurality belonging to a second set of timing paths and include a first common characteristic. The method includes improving the first set of timing paths based at least in part on an improvement to an individual timing path of the first set of timing paths.

Abstract: A technique improves the performance of an integrated circuit design by selectively replacing low Vt transistors with standard Vt transistors. The selection of gates for replacement may be based on a multi-path timing analysis. If a low Vt variant of a gate instance increases a path cycle time as compared to a standard Vt counterpart, the maximum of the path cycle times for all paths that include the low Vt variant and the maximum of the path cycle time for these paths with a standard Vt variant are calculated. If the maximum path cycle time for the path including the low Vt variant is greater than the maximum path cycle time for the path including the standard Vt variant, then that low Vt variant is substituted with a standard Vt variant. Thus, integrated circuit designs prepared in accordance with the invention may exhibit improved cycle times.