Patents by Inventor Sriram Sriniyasan

Sriram Sriniyasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Microelectronic package and method for a compression-based mid-level interconnect
    Patent number: 8440506
    Abstract: A microelectronic package includes first substrate (120) having first surface area (125) and second substrate (130) having second surface area (135). The first substrate includes first set of interconnects (126) having first pitch (127) at first surface (121) and second set of interconnects (128) having second pitch (129) at second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes third set of interconnects (236) having third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: May 14, 2013
    Assignee: Intel Corporation
    Inventors: Brent M. Roberts, Mihir K. Roy, Sriram Sriniyasan, Sridhar Narasimhan
  • MICROELECTRONIC PACKAGE AND METHOD FOR A COMPRESSION-BASED MID-LEVEL INTERCONNECT
    Publication number: 20120279059
    Abstract: A microelectronic package includes first substrate (120) having first surface area (125) and second substrate (130) having second surface area (135). The first substrate includes first set of interconnects (126) having first pitch (127) at first surface (121) and second set of interconnects (128) having second pitch (129) at second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes third set of interconnects (236) having third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.
    Type: Application
    Filed: July 11, 2012
    Publication date: November 8, 2012
    Inventors: Brent M. Roberts, Mihir K. Roy, Sriram Sriniyasan, Sridhar Narasimhan