Patents by Inventor Sriram Thyagarajan
Sriram Thyagarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240135988Abstract: Various implementations described herein are related to a device having a storage node with a bitcell. The device may have a first stage that performs a first write based on an internal bitline signal, a first write wordline signal and a second write wordline signal. The first stage outputs the internal bitline signal. The device may have a second stage that receives the internal bitline signal and performs a second write of the internal bitline signal to the bitcell. The device may have a third stage with write wordline ports and write bitline ports. The third stage provides the internal bitline signal based on a selected write wordline signal from a write wordline port of the write wordline ports and based on a selected bitline signal based on a write bitline port of the write bitline ports.Type: ApplicationFiled: October 20, 2022Publication date: April 25, 2024Inventors: Vianney Antoine Choserot, Andy Wangkun Chen, Yew Keong Chong, Sriram Thyagarajan
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Patent number: 11900995Abstract: Various implementations described herein are related to a method for accessing a bitcell in an array of bitcells with a wordline and a bitline. The method may perform a precharge operation on the bitline that precharges the bitline after a read cycle and before a write cycle. Also, the method may extend precharge time of the precharge operation between the read cycle and the write cycle, e.g., by modulating a wordline signal on the wordline with early cut-off of the wordline signal on the wordline during the read cycle.Type: GrantFiled: April 6, 2021Date of Patent: February 13, 2024Assignee: Arm LimitedInventors: Rajiv Kumar Sisodia, Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Ayush Kulshrestha, Munish Kumar
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Publication number: 20240012748Abstract: According to one implementation of the present disclosure, an integrated circuit includes comparator circuitry coupled to peripheral circuitry of a multiport memory and configured to transmit one or more data input signals or one or more write enable signals to respective memory outputs when a memory address collision is detected for one or more respective bitcells of the multi-port memory. In another implementation, a method comprises: detecting a read operation and a write operation to a same memory bitcell of a multiport memory in one clock cycle and in response to the detection, performing the read operation of a data input signal or a write enable signal of the multiport memory.Type: ApplicationFiled: July 8, 2022Publication date: January 11, 2024Inventors: Andy Wangkun Chen, Yew Keong Chong, Sriram Thyagarajan
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Publication number: 20230411351Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through an input/output circuit of the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings at least partially in an input/output circuitry of the memory macro unit based on the determined dimensions of the memory macro unit.Type: ApplicationFiled: May 24, 2022Publication date: December 21, 2023Inventors: Andy Wangkun Chen, Yew Keong Chong, Sriram Thyagarajan, Vivek Asthana, Ettore Amirante
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Publication number: 20230410896Abstract: Various implementations described herein are directed to a device having memory circuitry having multi-port bitcells, wherein each bitcell of the multi-port bitcells has a read-write port and a read port. The device may have read-write circuitry coupled to the read-write port, wherein the read-write circuitry has write-drive logic and read-sense logic that provide for at least one write and at least one read in a single clock cycle.Type: ApplicationFiled: June 20, 2022Publication date: December 21, 2023Inventors: Yew Keong Chong, Sriram Thyagarajan, Andy Wangkun Chen, Arjun Singh, Ayush Kulshrestha
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Patent number: 11837543Abstract: Various implementations described herein are related to various devices having a frontside power network with frontside supply rails and a backside power network with backside supply rails. The device may include intermixing architecture with transition vias that couple the frontside power network to the backside power network. The intermixing architecture may transition the frontside supply rails of the frontside power network to the backside supply rails of the backside power network.Type: GrantFiled: August 28, 2020Date of Patent: December 5, 2023Assignee: Arm LimitedInventors: Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Sony, Ettore Amirante, Ayush Kulshrestha
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Patent number: 11676656Abstract: Various implementations described herein are related to a device having memory circuitry with bitlines coupled to an array of bitcells. Also, the device may have first precharge circuitry that precharges the bitlines before a write cycle. Also, the device may have second precharge circuitry that precharges the bitlines after the write cycle.Type: GrantFiled: February 5, 2021Date of Patent: June 13, 2023Assignee: Arm LimitedInventors: Andy Wangkun Chen, Yew Keong Chong, Rajiv Kumar Sisodia, Sriram Thyagarajan
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Publication number: 20230136348Abstract: Various implementations described herein are directed to a device having memory control circuitry having global passgates and a read-write driver that provides a global read-write signal to the global passgates. The device may have sense amplifier circuitry with local-drivers and a sense amplifier driver that provides a sense amplifier enable signal to the local-drivers, wherein the local-drivers may include multiple buffers coupled to the sense amplifier driver in parallel.Type: ApplicationFiled: October 29, 2021Publication date: May 4, 2023Inventors: Sriram Thyagarajan, Yew Keong Chong, Munish Kumar, Andy Wangkun Chen, Rajiv Kumar Sisodia
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Patent number: 11631439Abstract: Various implementations described herein are directed to a device having memory control circuitry having global passgates and a read-write driver that provides a global read-write signal to the global passgates. The device may have sense amplifier circuitry with local-drivers and a sense amplifier driver that provides a sense amplifier enable signal to the local-drivers, wherein the local-drivers may include multiple buffers coupled to the sense amplifier driver in parallel.Type: GrantFiled: October 29, 2021Date of Patent: April 18, 2023Assignee: Arm LimitedInventors: Sriram Thyagarajan, Yew Keong Chong, Munish Kumar, Andy Wangkun Chen, Rajiv Kumar Sisodia
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Patent number: 11624777Abstract: Various implementations described herein are related to a method for constructing integrated circuitry and identifying input signal paths, internal signal paths and output signal paths associated with the integrated circuitry. The method may include generating a timing table for slew-load characterization of the input signal paths, the internal signal paths and the output signal paths. The method may include simulating corner points for the timing table, building diagonal points for the timing table based on the simulated corner points, and building remaining points for the timing table based on the simulated corner points and the diagonal points.Type: GrantFiled: April 23, 2020Date of Patent: April 11, 2023Assignee: Arm LimitedInventors: Sriram Thyagarajan, Pratik Ghanshambhai Satasia, Yew Keong Chong, Andy Wangkun Chen, Mouli Rajaram Chollangi
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Patent number: 11567741Abstract: Various implementations described herein are directed to a system and methods for memory compiling. For instance, a method may include selecting source corners from a memory compiler configuration and generating a standardized set of memory instances for the selected source corners. Also, the method may include deriving a reduced set of memory instances based on the standardized set of memory instances and building a memory compiler database for a compiler space based on the standardized set of memory instances and the reduced set of memory instances.Type: GrantFiled: June 11, 2020Date of Patent: January 31, 2023Assignee: Arm LimitedInventors: Mouli Rajaram Chollangi, Sriram Thyagarajan, Hongwei Zhu, Yew Keong Chong, Pratik Ghanshambhai Satasia
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Patent number: 11557583Abstract: Various implementations described herein refer to a device having logic circuitry with transistors and gate lines. The device may include a backside power network having buried supply rails with at least one buried supply rail having a continuity break. The transistors may be arranged in a cell architecture having an N-well break with the gate lines passing through the N-well break and the continuity break.Type: GrantFiled: September 10, 2020Date of Patent: January 17, 2023Assignee: Arm LimitedInventors: Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Sony
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Publication number: 20220319586Abstract: Various implementations described herein are related to a method for accessing a bitcell in an array of bitcells with a wordline and a bitline. The method may perform a precharge operation on the bitline that precharges the bitline after a read cycle and before a write cycle. Also, the method may extend precharge time of the precharge operation between the read cycle and the write cycle, e.g., by modulating a wordline signal on the wordline with early cut-off of the wordline signal on the wordline during the read cycle.Type: ApplicationFiled: April 6, 2021Publication date: October 6, 2022Inventors: Rajiv Kumar Sisodia, Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Ayush Kulshrestha, Munish Kumar
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Publication number: 20220309225Abstract: Various implementations described herein are directed to a method for identifying pre-routed metal lines in a higher layer of a multi-layered structure. The method may recognize gaps in the pre-routed metal lines of the higher layer, and also, the method may automatically fill the gaps with conductive stubs to modify the pre-routed metal lines in the higher layer as a continuous metal line with an extended length.Type: ApplicationFiled: March 23, 2021Publication date: September 29, 2022Inventors: Sriram Thyagarajan, Yew Keong Chong, Sony, Andy Wangkun Chen
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Publication number: 20220293522Abstract: Various implementations described herein are directed to a method for routing buried power rails underneath a memory instance. The method may identify first rails of the buried power rails disposed in a first layer and second rails of the buried power rails disposed perpendicular to the first rails in a second layer. The method may identify long rails of the first rails with a first length and short rails of the first rails with a second length that is less than the first length. The method may separately couple the long rails and the short rails to the second rails with vias that extend between the first layer and the second layer.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Inventors: Sriram Thyagarajan, Ettore Amirante, Andy Wangkun Chen, Yew Keong Chong, Sony .
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Patent number: 11443777Abstract: Various implementations described herein refer to a device having backside power rails including first backside power rails that supply a core voltage to memory logic and second backside power rails that supply a periphery voltage to control logic. In some implementations, at least one first backside power rail may have a rail break that interrupts continuity so as to allow at least one second backside power rail to supply the periphery voltage to the control logic.Type: GrantFiled: September 11, 2020Date of Patent: September 13, 2022Assignee: Arm LimitedInventors: Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Sony, Ettore Amirante, Ayush Kulshrestha
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Publication number: 20220254411Abstract: Various implementations described herein are related to a device having memory circuitry with bitlines coupled to an array of bitcells. Also, the device may have first precharge circuitry that precharges the bitlines before a write cycle. Also, the device may have second precharge circuitry that precharges the bitlines after the write cycle.Type: ApplicationFiled: February 5, 2021Publication date: August 11, 2022Inventors: Andy Wangkun Chen, Yew Keong Chong, Rajiv Kumar Sisodia, Sriram Thyagarajan
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Patent number: 11380384Abstract: Various implementations described herein are related to a device having memory circuitry with a bitcell array. The device may include a frontside power network that is coupled to the bitcell array, and the device may include a backside power network that provides power to the bitcell array. The device may include transition vias that couple the backside power network to the frontside power network, and the backside power network may provide power to the bitcell array by way of the transition vias being coupled to the frontside power network.Type: GrantFiled: August 28, 2020Date of Patent: July 5, 2022Assignee: Arm LimitedInventors: Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Sony, Ettore Amirante, Ayush Kulshrestha
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Patent number: 11322197Abstract: Various implementations described herein are related to a device having wordline drivers coupled to a core array. The device may have backside power network with buried power rails. The device may have header logic coupled to power supply connections of the wordline drivers by way of the buried power rails, and the header logic may be used to power-gate the wordline drivers.Type: GrantFiled: October 21, 2020Date of Patent: May 3, 2022Assignee: Arm LimitedInventors: Rajiv Kumar Sisodia, Andy Wangkun Chen, Ayush Kulshrestha, Sony, Sriram Thyagarajan, Yew Keong Chong
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Publication number: 20220122656Abstract: Various implementations described herein are related to a device having wordline drivers coupled to a core array. The device may have backside power network with buried power rails. The device may have header logic coupled to power supply connections of the wordline drivers by way of the buried power rails, and the header logic may be used to power-gate the wordline drivers.Type: ApplicationFiled: October 21, 2020Publication date: April 21, 2022Inventors: Rajiv Kumar Sisodia, Andy Wangkun Chen, Ayush Kulshrestha, Sony, Sriram Thyagarajan, Yew Keong Chong