Abstract: A divider circuit receives an input signal and at least one phase adjustment control signal and supplies a phase adjustable output signal. The divider circuit includes a state machine providing N states, with no phase adjustment, to provide as the output signal the input signal divided by N. Each state of the state machine lasts for one period of the input signal. The divider circuit adjusts the phase of the output signal by changing the number of states that occur in one period of the output signal. In response to a control signal to decrement the phase of the output signal, the state machine skips at least one state for one period of the output signal. In response to a control signal to increment the phase of the output signal, the state machine inserts one or more states for one period of the output signal.